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w wm8777 24-bit, 192khz av receiver on-a-chip wolfson microelectronics plc www.wolfsonmicro.com pre-production, january 2005, rev 3.0 copyright ? 2005 wolfson microelectronics plc description the wm8777 is a high performance, multi-channel audio codec. the wm8777 is ideal for surround sound processing applications for home hi-fi, automotive and other audio visual equipment. a s/pdif transceiver with 4-channel input mux is included. analogue domain bass management processing, and front channel analogue tone control facilities are provided. a stereo 24-bit multi-bit sigma delta adc is used with a six stereo channel input selector. each channel has analogue domain mute and programmable gain control. sampling rates from 8khz to 192khz are supported. four stereo 24-bit multi-bit sigma delta dacs are provided, which may be used to support up to 7.1 channel operation. if preferred, 5.1 operation may be chosen, with the spare stereo dac used to support an aux remote room. sampling rates from 8khz to 192khz are supported. each dac channel has independent digital volume and mute control. a set of input multiplexers allows switching of an external 5.1 analogue input, or bypass channel stereo analogue input into the signal path. the front channel analogue signals may be looped out of the chip prior to each master volume control, and external filtering applied in order to select treble and bass filter characteristics. adjustment of tone controls is then achieved using on-chip gain adjust amplifiers, addressed via the control interface. analogue bass management support is provided, plus analogue stereo mix down options. the device is controlled via a serial interface giving access to all features including channel selection, volume controls, tone controls, mutes, de-emphasis and power management facilities. the device is available in a 100-pin lqfp package. features ? av receiver on-a-chip with 8 dacs and 2 adcs ? integrated s/pdif/iec60958/aes3 transceiver ? analogue bass management and stereo mixdown support ? analogue tone controls for front 3 channels ? master volume control on each dac channel with gain range of +20db to -100db in 1db steps ? audio performance ? 108db snr (a weighted @ 48khz) dac ? 102db snr (a weighted @ 48khz) adc ? 110db snr (a weighted) analogue volume control ? dac sampling frequency: 8khz C 192khz ? adc sampling frequency: 8khz C 192khz ? 3-wire spi or 2-wire mpu serial control interface with read back. ? master or slave clocking mode ? programmable format audio data interface modes ? four independent stereo dac outputs with independent digital volume controls ? integrated stereo headphone amplifier with source select ? 5.1 channel analogue input prior to the tone controls, bass management and stereo mix down functions. ? six stereo input adc mux with analogue gain adjust from +24db to C21db in 0.5db steps ? 5v analogue, 2.7v to 3.6v digital supply operation applications ? surround sound av processors and hi-fi systems
wm8777 pre-production w pp rev 3.0 january 2004 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 absolute maximum ratings.........................................................................6 recommended operating conditions .....................................................6 electrical characteristics ......................................................................7 terminology .......................................................................................................... 10 supply current .............................................................................................11 device description .......................................................................................12 introduction ......................................................................................................... 12 analogue tone controls ................................................................................. 13 bass management................................................................................................. 19 headphone output .............................................................................................. 20 output powerdown............................................................................................ 21 digital audio interface routing options................................................... 22 control interface operation ........................................................................ 24 control interface timing ................................................................................ 27 master clock ........................................................................................................ 29 audio sampling rates and audio interfaces ............................................. 30 audio interface formats.................................................................................. 35 digital audio interface control registers ............................................. 38 powerdown modes ............................................................................................. 39 master clock and phase locked loop......................................................... 42 s/pdif transceiver features........................................................................... 45 s/pdif transmitter............................................................................................... 47 s/pdif receiver...................................................................................................... 50 dac control registers ..................................................................................... 56 output select and enable control ............................................................. 65 adc control registers ..................................................................................... 66 limiter / automatic level control (alc)...................................................... 68 software register reset ................................................................................ 72 register map...................................................................................................73 digital filter characteristics ...............................................................95 dac filter responses .................................................................................96 adc high pass filter ....................................................................................97 digital de-emphasis characteristics........................................................... 98 applications information .........................................................................99 external analogue input circuit configuration ................................... 99 external s/pdif input circuit configuration ......................................... 100 recommended analogue output external components.................... 101 important notice ........................................................................................103 address: ................................................................................................................ 103
pre-production wm8777 w pp rev 3.0 january 2005 3 pin configuration ordering information device temperature range package moisture sensitivity level peak soldering temperature wm8777seft/v -25 o c to +85 o c 100-pin tqfp msl3 240 c
wm8777 pre-production w pp rev 3.0 january 2004 4 pin description pin name type description 1 pgnd supply pll ground supply 2 pvdd supply pll positive supply 3 clkout digital output pll output or crystal oscillator output 4 pdataop digital output primary audio interface data output (adc) 5 pdataip1 digital input primary audio interface data input 1 (dac1) 6 pdataip2 digital input primary audio interface data input 2 (dac2) 7 pdataip3 digital input primary audio interface data input 3 (dac3) 8 pdataip4 digital input primary audio interface data input 4 (dac4) 9 pdataiplrc digital input/output dac left/right word clock 10 pdataoplrc digital input/output adc left/right word clock 11 pbclk digital input/output adc and dac audio interface bit clock 12 mclk digital input/output master dac and adc clock; 128, 192, 256, 384, 512, 768fs or 1152fs (fs = word clock freq) 13 sdout digital output serial interface output data 14 dvdd supply digital positive supply 15 dgnd supply digital negative supply 16 csb digital input serial interface latch signal (5v tolerant) 17 sclk digital input serial interface clock (5v tolerant) 18 sdin digital input serial interface data (5v tolerant) 19 ain1l analogue input channel 1 left input multiplexor virtual ground 20 ain1r analogue input channel 1 right input multiplexor virtual ground 21 ain2l analogue input channel 2 left input multiplexor virtual ground 22 ain2r analogue input channel 2 right input multiplexor virtual ground 23 ain3l analogue input channel 3 left input multiplexor virtual ground 24 ain3r analogue input channel 3 right input multiplexor virtual ground 25 ain4l analogue input channel 4 left input multiplexor virtual ground 26 ain4r analogue input channel 4 right input multiplexor virtual ground 27 ain5l analogue input channel 5 left input multiplexor virtual ground 28 ain5r analogue input channel 5 right input multiplexor virtual ground 29 ain6l analogue input channel 6 left input multiplexor virtual ground 30 ain6r analogue input channel 6 right input multiplexor virtual ground 31 ainopl analogue output left channel multiplexor output 32 ainvgl analogue input left channel multiplexor virtual ground 33 ainvgr analogue input right channel multiplexor virtual ground 34 ainopr analogue output right channel multiplexor output 35 recl analogue output left channel input mux select output 36 recr analogue output right channel input mux select output 37 avddadc supply analogue positive supply for adc 38 refadcp analogue output adc reference buffer decoupling pin; 10uf external decoupling 39 vmidadc analogue output adc midrail divider decoupling pin; 10uf external decoupling 40 agndadc supply analogue negative supply and substrate connection for adc 41 refadcn supply adc ground reference 42 dacrefp1 supply dac positive reference supply 43 dacrefn1 supply dac ground reference 44 vmiddac1 analogue output dac midrail decoupling pin ; 10uf external decoupling 45 rauxsop analogue output right aux/rear channel summer output 46 rauxbmin analogue input right aux/rear channel bass managed filtered input 47 lauxsop analogue output left aux/rear channel summer output 48 lauxbmin analogue input left aux/rear channel bass managed filtered input 49 auxr analogue output dac aux or rear channel right output 50 auxl analogue output dac aux or rear channel left output
pre-production wm8777 w pp rev 3.0 january 2005 5 pin name type description 51 rrbmin analogue input right surround channel bass managed filtered input 52 rsursop analogue output right surround channel summer output 53 surr analogue output dac surround channel right output 54 lrbmin analogue input left surround channel bass managed filtered input 55 lsursop analogue output left surround channel summer output 56 surl analogue output dac surround channel left output 57 aux3r analogue input 3.1 multiplexor channel 3 right virtual ground input 58 aux3l analogue input 3.1 multiplexor channel 3 left virtual ground input 59 lfe analogue output dac lfe channel right output 60 lfeve analogue input lfe channel summer virtual earth 61 lfesum analogue output lfe channel summer output 62 lfesop analogue output lfe channel summer output 63 avdddac supply analogue positive supply for dac 64 agnddac supply analogue negative supply and substrate connection for dac 65 hphoner analogue output headphone channel right output 66 hphonel analogue output headphone channel left output 67 aux2r analogue input 3.1 multiplexor channel 2 right virtual ground input 68 aux2l analogue input 3.1 multiplexor channel 2 left virtual ground input 69 cntr analogue output dac centre channel right output 70 cntsop analogue output centre front channel summer output 71 cin3 analogue input centre channel bass management filter input 72 cin2 analogue input centre channel bass filter input 73 cin1 analogue input centre channel treble filter input 74 frontr analogue output dac front channel right output 75 rin3 analogue input right front channel bass management filter input 76 rin2 analogue input right front channel bass filter input 77 rin1 analogue input right front channel treble filter input 78 rsumop analogue output right front channel summer output 79 frontl analogue output dac front channel left output 80 lin3 analogue input left front channel bass management filter input 81 lin2 analogue input left front channel bass filter input 82 lin1 analogue input left front channel treble filter input 83 lsumop analogue output left front channel summer output 84 aux1r analogue input 3.1 multiplexor channel 1 right virtual ground input 85 aux1l analogue input 3.1 multiplexor channel 1 left virtual ground input 86 vmiddac2 analogue output dac midrail decoupling pin ; 10uf external decoupling 87 dacrefn2 supply dac ground reference 88 dacrefp2 supply dac positive reference supply 89 gpio1 digital input/output selectable i/o (s/pdif input, status flag output or adcmclk) 90 gpio2 digital input/output selectable i/o (s/pdif input, status flag output, or pdataopbclk) 91 gpio3 digital input/output selectable i/o (s/pdif input or status flag output) 92 gpo/mode digital input/output selectable i/o (state at reset determines control interface type) 93 spin digital input s/pdif input 94 spdifop digital output s/pdif output 95 sbclk digital input/output secondary audio interface bit clock 96 slrc digital input/output secondary audio interface left/right clock 97 sdataop digital output secondary audio interface output data 98 sdataip digital input secondary audio interface input data 99 xto crystal op crystal oscillator output 100 xti digital input crystal oscillator or external clock inputs
wm8777 pre-production w pp rev 3.0 january 2004 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. as per specification ipc/jedec j-std-020b, this product requires specific storage conditions prior to surface mount assembly. i t has a moisture sensitivity level of 3 and as such will be supplied in vacuum-sealed moisture barrier bags, with an out of bag exposure time limit of 1 week at less than 30 c / 60% rh. condition min max digital supply voltage -0.3v +3.63v analogue supply voltage -0.3v +7v voltage range digital inputs (sdin, sclk, csb) dgnd -0.3v +7v voltage range digital inputs (mclk, din[3:0], pdataoplrc, pdataiplrc and pbclk) dgnd -0.3v dvdd + 0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency 37mhz operating temperature range, t a -25 c +85 c storage temperature -65 c +150 c note: 1. analogue and digital grounds must always be within 0.3v of each other. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd 2.7 3.6 v analogue supply range avdddac,avddacd, pvdd 4.5 5.5 v analogue reference range vrefp 4.5 5.5 ground agnddac, agndadc, pgnd, dgnd, vrefn 0 v difference dgnd to agnddac/agndadc/pll gnd -0.3 0 +0.3 v
pre-production wm8777 w pp rev 3.0 january 2005 7 electrical characteristics test conditions avdddac = 5v, avddadc=5v, dvdd = 3.3v, agnddac = 0v, agndadc = 0, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, adc/dac in slave mode unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels ( cmos levels) input low level v il 0.3 x dvdd v input high level v ih 0.7 x dvdd v input leakage current 0.2 a input capacitance 5 pf output low v ol i ol =1ma 0.1 x dvdd v output high v oh i oh -1ma 0.9 x dvdd v analogue reference levels v vmid (dac) vrefp/2 v reference voltage v vmid (adc) avddadc/2 v r vmid (dac) vrefp to vmid and vmid to vrefn 50k ? potential divider resistance r vmid (adc) avddadc to vmid and vmid to agndadc 50k ? dac performance (load = 10k ? , 50pf) to pins l/rsumop, cntsop, lfesop, l/rsurop, l/rauxsop 0dbfs full scale output voltage 1.0 x vrefp/5 vrms snr (note 1,2) a-weighted, @ fs = 48khz 100 108 db snr (note 1,2) a-weighted @ fs = 96khz 108 db dynamic range (note 2) dnr a-weighted, -60db full scale input 100 108 db total harmonic distortion (thd) 1khz, 0dbfs -96 -90 db dac channel separation 110 db dac mute attenuation 1khz input, 0db gain 88 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mvpp 45 db dac digital volume dac digital volume control range -127.5 0 db dac digital volume step size 0.5 db adc performance input signal level (0db) 1.0 x avddadc/5 vrms snr (note 1,2) a-weighted, 0db gain @ fs = 48khz 96 102 db snr (note 1,2) a-weighted, 0db gain @ fs = 96khz 100 db dynamic range (note 2) a-weighted, -60db full scale input 96 102 db 1khz, 0dbfs -89 db total harmonic distortion (thd) 1khz, -1dbfs -94 -87 db adc channel separation 1khz input 85 db programmable gain step size 0.5 db programmable gain range (analogue) 1khz input -21 +24 db programmable gain range (digital) 1khz input -103 -21.5 db mute attenuation 1khz input, 0db gain 82 db
wm8777 pre-production w pp rev 3.0 january 2004 8 test conditions avdddac = 5v, avddadc=5v, dvdd = 3.3v, agnddac = 0v, agndadc = 0, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, adc/dac in slave mode unless otherwise stated. parameter symbol test conditions min typ max unit 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mvpp 45 db input resistance (ain1 -> ain6) 20 k ? input capacitance (ain1 -> ain6) 10 pf adc pga output to analogue output (l/rsumop, cntsop, lfesop, l/rsurop, l/rauxsop) (load=10k ? , 50pf, gain = 0db) bypass mode 0db full scale output voltage 1.0 x avdddac/5 vrms snr (note 1) 100 105 db 1khz, 0db -93 db thd 1khz, -3db -95 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mv 45 db mute attenuation 1khz, 0db 88 db analogue input (ain6) to analogue output (frontl, frontr) (load=10k ? , 50pf, gain = 0db) bypass mode 0db full scale output voltage 1.0 x avdddac/5 vrms snr (note 1) 100 105 db 1khz, 0db -93 db thd 1khz, -3db -95 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mv 45 db mute attenuation 1khz, 0db 88 db adc pga to rec output 0db full scale output voltage 1.0 x avdddac/5 vrms snr (note 1) 100 104 db 1khz, 0db -87 db thd 1khz, -3db -89 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mv 45 db mute attenuation 1khz, 0db 88 db l/rsumop to rec output 0db full scale output voltage 1.0 x avdddac/5 vrms snr (note 1) 97 100 db thd 1khz, 0db -94 db 1khz, -3db -96 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mv 45 db mute attenuation 1khz, 0db 88 db l/raux input to analogue output (l/rsumop, cntsop, lfesop, l/rsurop, l/rauxsop) (load=10k ? , 50pf, gain = 0db) 0db full scale output voltage 1.0 x avdddac/5 vrms snr (note 1) 103 107 db 1khz, 0db -94 db thd 1khz, -3db -96 db 1khz 100mvpp 50 db power supply rejection ratio psrr 20hz to 20khz 100mv 45 db mute attenuation 1khz, 0db 88 db
pre-production wm8777 w pp rev 3.0 january 2005 9 test conditions avdddac = 5v, avddadc=5v, dvdd = 3.3v, agnddac = 0v, agndadc = 0, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, adc/dac in slave mode unless otherwise stated. parameter symbol test conditions min typ max unit volume controls (frontl, frontr, cntr, lfe, surr, surl, auxl, auxr, hphoner, hphonel) analogue output volume gain step size 0.5 1 1.5 db analogue output volume gain range 1khz input -88 +20 db analogue output volume mute attenuation 1khz input, 0db gain 88 db analogue tone volume step size 1 db analogue bass management and tone controls treble range adjustment -10 +10 db treble step size 1 db bass range adjustment -10 +10 db bass step size 1 db headphone amplifier at 0db volume (load=16 ? , at 1vrms) headphone output level 1.0 vrms thd -70 db snr -102 db headphone amplifier at 0db volume (load=32 ? , at 1vrms) headphone output level 1.0 vrms thd -78 db snr -102 db s/pdif transceiver jitter on recovered clock (rms period jitter) 50 ps s/pdif input levels cmos mode input low level v il 0.3 x dvdd v input high level v ih 0.7 x dvdd v input capacitance 1.25 pf input frequency 36 mhz s/pdif input levels comparator mode input capacitance 1.31 pf input resistance 18 ? input frequency 25 mhz input amplitude 200 0.5 x dvdd mv pll period jitter 80 ps(rms) xtal input xti low level vx il 0 557 mv input xti high level vxi h 853 mv input xti capacitance c xj 3.32 4.491 pf input xti leakage ix leak 28.92 38.96 ma output xto low vx ol 15pf load capacitors 86 278 mv output xto high vx oh 15pf load capacitors 1.458 1.942 v notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured a weighted. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance).
wm8777 pre-production w pp rev 3.0 january 2004 10 terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 6. pass-band ripple - any variation of the frequency response in the pass-band region.
pre-production wm8777 w pp rev 3.0 january 2005 11 supply current the supply current of the wm877 depends on the operating mode. for example, the supply current is lower when the device is used for playback-only (adc off) or recording-only (dacs off). the supply currents for various operating modes are shown in table 1 below. supply current mode description avdddac avddadc pvdd dvdd total unit on power-up, no clks applied 2.81 1.89 0.30 0.39 5.39 ma on power-up, clks applied 2.81 1.89 0.30 1.70 6.70 ma adc 2.71 38.86 0.30 5.80 47.67 ma all dacs 55.35 1.90 0.30 18.61 76.16 ma adc, all dacs 53.45 38.69 0.30 22.4 114.84 ma adc, all dacs, osc 53.44 38.70 1.12 22.4 115.66 ma adc, all dacs, osc, pll 53.38 38.62 3.74 28.65 124.39 ma adc, all dacs, osc, pll, s/pdif 53.38 38.62 3.43 29.89 125.32 ma adc, all dacs, osc, pll, s/pdif, tone 87.53 38.53 3.43 29.99 159.48 ma adc, all dacs, osc, pll, s/pdif, tone, hp (16 ohm) 146.60 38.42 3.44 29.99 218.45 ma power-down, no clks applied 0.028 0.172 0.30 0.39 0.89 ma power-down, clks applied 0.028 0.172 0.30 1.60 2.10 ma software reset 2.80 1.88 0.3 0.95 5.93 ma table 1 supply current for functional blocks notes: 1. dac analogue supply (avdddac) = 5v. 2. adc analogue supply (avddadc) = 5v. 3. pll analogue supply (pvdd) = 5v. 4. digital supply (dvdd) = 3.3v.
wm8777 pre-production w pp rev 3.0 january 2004 12 device description introduction wm8777 is a complete 8-channel dac, 2-channel adc audio codec, with integrated s/pdif transceiver, analogue tone controls and bass management including analogue volume controls on each channel. the device is implemented as four separate stereo dacs and a stereo adc with flexible input multiplexer, in a single package and controlled by a single interface. the four stereo channels may either be used to implement a 5.1 channel surround system, with additional stereo channel for a stereo mix down channel, or for a complete 7.1 channel surround system. an analogue bypass path option is available, to allow stereo analogue signals from any of the 8 stereo inputs to be sent to the stereo outputs via the main volume controls. this allows a purely analogue input to analogue output high quality signal path to be implemented if required. this would allow, for example, the user to play back a 5.1 channel surround movie through 6 of the dacs, whilst playing back a separate analogue or digital signal into a remote room installation. the wm8777 has two digital audio interfaces. the primary audio interface has separate inputs for each stereo dac, and one data output which can output digital data from the adc, received s/pdif data or data received from the secondary audio interface. data directed to dac1 is also directed to the s/pdif transmitter. the secondary audio interface has a single data input and a single data output. the input data can be output over the primary audio interface, or converted into s/pdif format and output over the s/pdif transmitter. both audio interfaces may be configured to operate in either master or slave mode and support right justified, left justified and i 2 s interface formats along with a highly flexible dsp serial port interface. the input multiplexor to the adc is configured to allow large signal levels to be input to the adc, using external resistors to reduce the amplitude of larger signals to within the normal operating range of the adc. the adc input pga also allows input signals to be gained up to +24db and attenuated down to -21db. this allows the user maximum flexibility in the use of the adc. a selectable stereo record output is also provided on recl/r. it is intended that the recl/r outputs are only used to drive a high impedance buffer. each dac has its own digital volume control. the digital volume control changes can be made in 0.5db steps. in addition a zero cross detect circuit is provided for each dac. the digital volume control detects a transition through the zero point before updating the volume. this minimises audible clicks and zipper noise as the gain values change. in addition to this there is an analogue volume control on each of the tone outputs, with a zero cross detect circuit. the analogue volume control changes can be made in 1db steps. when analogue volume zero-cross detection is enabled the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. additionally, 6 of the dac outputs incorporate an input selector and mixer allowing an external 6 channel, or 5.1 channel signal, to be either switched into the signal path in place of the dac signal or mixed with the dac signal. control of internal functionality of the device is by 3-wire spi or 2-wire serial control interface selectable by the state of the gpo/mode pin on power up. the control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. csb, sclk, and sdin are 5v tolerant with ttl input thresholds, allowing the wm8777 to be used with dvdd = 3.3v and be controlled by a controller with 5v output. operation using a system clock of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. in slave mode selection between clock rates is automatically controlled. in master mode the master clock to sample rate ratio is set by control bits paiftx_rate and paifrx_rate. the adc and dac may run at different rates within the constraint of a common master clock. for example with master clock at 24.576mhz, a dac sample rate of 96khz (256fs mode) and an adc sample rate of 48khz (512fs mode) can be accommodated. sample rates (fs) from less than 8ks/s up to 192ks/s are allowed, provided the appropriate system clock is input.
pre-production wm8777 w pp rev 3.0 january 2005 13 analogue tone controls facilities are provided for implementation of analogue treble and bass tone controls on each of the front left, right and centre channels. external r and c values are used to set the corner frequencies of these tone control functions, allowing the system builder to choose the required responses. adjustment of the amplitude of the required tone response is made electronically by writing the required gain or attenuation value into the wm8777 over the serial control interface. maximum boost or attenuation of tone control values of +/-10db in 1db steps is provided. a tone control bypass path is provided, plus input summing paths for rear (i.e. surround l/r), centre and lfe channels, to allow for creation of a stereo mix-down signal when only two speakers are supported. each of these mix-down paths has independent gain adjust from 0db to -6db in 1db steps. an analogue input bypass path is also provided. this allows ain6l and ain6r to be output on the frontl and frontr output channels making use of the volume controls if required. in order to provide sufficient headroom for cases where significant amounts of analogue treble or bass boost have been applied, a gain attenuation control is provided in the summing stage after the tone adjust pgas. this allows attenuation of -6db, -12db or -18db to be applied. re-adjustment of the nominal 0db signal level may then be made in the following volume control stage as required. pad pad pad pad bass filter treble filter bass managed signal bass cut +/-10db treble boost tone control bypass main volume control +20db to -100db 0, -6, -12, -18db bass boost bass management filter bypass aux input dac pad xsumop xin3 xin2 xin1 frontl/r treble cut bass management pad rearl/r center lfe stereo mix-down inputs no-sub option ain6l/r 0 to -6db figure 1 tone control configuration - front left/right (single channel shown) pad pad pad pad bass filter treble filter bass managed signal bass cut +/-10db treble boost tone control bypass main volume control +20db to -100db 0, -6, -12, -18db bass boost bass management filter bypass aux input dac pad cntsumop cin3 cin2 cin1 cntr treble cut bass management pad lfe no-sub option 0 to -6db to front l/r figure 2 tone control configuration - centre channel
wm8777 pre-production w pp rev 3.0 january 2004 14 mixer control control of the front channel signal paths is via five software registers. the first three registers control both the front left and right channels whilst the remaining two control the centre channel. when only two speakers are available a stereo mix-down signal can be created by setting the rear, cntr and lfe bits of the appropriate register. control of the tone characteristics for a channel is determined by writing to the xtrbl and xbass register bits (where x implies either front l/r or centre channel). the tone controls work by adding/subtracting high/low-pass filtered signal content to the nominal 0db bass-managed signal. thus when using the tone controls, the xbm bit should also be set. note also that cut and boost cannot be applied simultaneously. if both bits are set, the tone control signal path will be bypassed but the amplifiers will remain enabled. to avoid pop-noises during dynamic tone control it is recommending that this method is used to disable the tone control signal path. setting both bits low disables the path, however it will also cause the amplifiers to power down. the mixer control registers (ftrbl, fbass, ctrbl and cbass) share the zero-cross detect circuit used by the analogue volume control. thus the zcen enable bit for a particular channel can be used to determine whether or not the tone control signal path select signals are updated only on a zero- cross condition. the bypass path is selected by setting the fbyp bit for the front l/r channels and the cbyp bit for the centre channel. the centre, rear and lfe channels can all be independently summed into the front l/r channels by setting the cntr, rear and flfe bits respectively. each of these signal paths has independent gain control from 0 to -6db, adjustable in 1db steps. these gains are determined by writing to the attenuation registers cntrgain, reargain and flfegain respectively. the lfe channel can also be summed into the front centre channel by setting the clfe bit. this path also has independent gain control from 0 to -6db, controlled by writing to the clfegain register. register address bit label default description 1:0 ftrbl[1:0] 00 control treble boost and cut:- 00 = both off ( amps disabled) 01 = treble cut 10 = treble boosted 11 = both off (amps enabled) 3:2 fbass[1:0] 00 controls bass boost and cut:- 00 = both off (amps disabled) 01 = bass cut 10 = bass boosted 11 = both off (amps enabled) 4 fbm 0 bass managed signal path select 0 = open 1 = closed 5 fbyp 0 tone control bypass signal path select 0 = open 1 = closed (22h) front mixer control 1 6 ain6 0 0 = ain6 not selected 1 = ain6 applied to front channels (23h) front mixer control 2 2:0 flfegain[2:0] 000 front lfe gain: 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db
pre-production wm8777 w pp rev 3.0 january 2005 15 register address bit label default description 3 flfe 0 lfe signal path select 0 = open 1 = closed 6:4 cntrgain[2:0] 000 front cntr gain: 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db 7 cntr 0 centre signal path mix 0 = open 1 = closed 2:0 reargain[2:0] 000 front rear gain: 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db (24h) front mixer control 3 3 rear 0 rear signal path mix 1:0 ctrbl[1:0] 00 control treble boost and cut: 00 = both off 01 = treble cut 10 = treble boosted 11 = both off 3:2 cbass[1:0] 00 controls bass boost and cut:- 00 = both off 01 = bass cut 10 = bass boosted 11 = both off 4 cbm 0 bass managed signal path select 0 = open 1 = closed (25h) center mixer control 1 5 cbyp 0 tone control bypass signal path select 0 = open 1 = closed 2:0 clfegain[2:0] 000 center lfe gain:- 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db (26h) center mixer control 2 3 clfe 0 lfe signal path select 0 = open 1 = closed table 2 output mixer control registers
wm8777 pre-production w pp rev 3.0 january 2004 16 tone control gain the amplitude of the tone response is controlled by writing gain values to the appropriate gain registers. the front left and right channels share gain registers, whilst the centre channel may be controlled independently. table 3 shows how the attenuation levels for the tone control blo cks are selected from the 4-bit code words. the tone control attenuation registers share the zero-cross detect circuit used by the analogue volume control. thus the zcen enable bit for a particular channel can be used to determine whether or not the treble/bass attenuation registers for that channel are updated only on a zero-cross condition. cut/boost code[3:0] attenuation level 0000 +1db 0001 +2db . . . . boost 1001 +10db 0000 -1db 0001 -2db . . . . cut 1001 -10db table 3 tone control attenuation levels
pre-production wm8777 w pp rev 3.0 january 2005 17 register address bit label default description 3:0 fbass[3:0] 0000 gain control for bass boost/cut (28h) front bass control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain front bass in intermediate latch (no change to output) 1 = store gain front bass and update attenuation on all channels. 3:0 ftreb[3:0] 0000 gain control for bass boost/cut (29h) front treble control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain front treble in intermediate latch (no change to output) 1 = store gain front treble and update attenuation on all channels. 3:0 cbass[3:0] 0000 gain control for bass boost/cut (2ah) center bass control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain center bass in intermediate latch (no change to output) 1 = store gain center bass and update attenuation on all channels. 3:0 ctreb[3:0] 0000 gain control for bass boost/cut (2bh) center treble control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain center treble in intermediate latch (no change to output) 1 = store gain center treble and update attenuation on all channels. table 4 tone control gain registers tone control pre-gain the tone pre-gain is applied directly before the analogue volume control for a channel. this is to allow scaling of the channel response prior to the overall channel volume control. each of the front right, left and centre channels accept their own 2-bit gain code to determine to amount of attenuation applied. the attenuation levels are given in table 5. pre-gain[0:1] attenuation 00 0db 01 -6db 10 -12db 11 -18db table 5 tone control pre-gain attenuation
wm8777 pre-production w pp rev 3.0 january 2004 18 register address bit label default description 1:0 cntp[1:0] 00 pregain control for cntr control channel 00 = 0db attenuation 01 = -6db attenuation 10 = -12db attenuation 11 = -18db attenuation 3:2 ftrp[1:0] 00 pregain control for frontr tone control channel 00 = 0db attenuation 01 = -6db attenuation 10 = -12db attenuation 11 = -18db attenuation 5:4 ftlp[1:0] 00 pregain control for frontl tone control channel 00 = 0db attenuation 01 = -6db attenuation 10 = -12db attenuation 11 = -18db attenuation 6 updatec 0 controls simultaneous update of all attenuation latches 0 = store pregain cntr in intermediate latch (no change to output) 1 = store pregain cntr and update attenuation on all channels. 7 updater 0 controls simultaneous update of all attenuation latches 0 = store pregain right in intermediate latch (no change to output) 1 = store pregain right and update attenuation on all channels. (2ch) mixer pregain 8 updatel 0 controls simultaneous update of all attenuation latches 0 = store pregain left in intermediate latch (no change to output) 1 = store pregain left and update attenuation on all channels. table 6 mixer pre-gain registers
pre-production wm8777 w pp rev 3.0 january 2005 19 bass management support is provided for bass management in the analogue domain. this might be used either in the case where a partnering dsp has insufficient mips to support all required functions, or where an analogue multi-channel input is required to be processed for use with small bass-limited speakers. provision is made for single pole high pass filtering of each front, centre, surround or rear channel, using a single external capacitor. the value of this capacitor may be chosen to set the required high- pass corner frequency, typically the dolby recommended 100hz value being preferred. use of extra external fet switches would allow the system builder to adjust this corner frequency in the system. to create the subwoofer channel signal, each of up to all 6 channels is summed into the lfe channel using external discrete summing resistors, and the entire summed subwoofer signal then low-pass band-limited using a further user selectable external capacitor value. this allows the gain from each individual channel, and the overall bass corner response to be selected. following this summing stage, an integrated volume control allows the overall level of the subwoofer channel to be set. pad +20db to -100db lfe lfeve pad pad +20db to -100db auxr rauxbmin pad pad +20db to -100db auxl lauxbmin pad pad +20db to -100db surr rrbmin pad pad +20db to -100db surl lrbmin pad pad lfesum dac bypass aux + pad lsumop dac bypass aux + pad rsumop dac bypass aux + pad cntsop dac bypass aux + pad lfesop dac bypass aux + pad lsurop dac bypass aux + pad rsurop dac bypass + pad lauxop dac bypass + pad rauxsop to centre tone network to front right tone network to front left tone network to front channels 100hz highpass 100hz lowpass 100hz highpass 100hz highpass (or 10hz if no bass management) 100hz highpass (or 10hz if no bass management) figure 3 bass management configuration
wm8777 pre-production w pp rev 3.0 january 2004 20 bass management bypass signal paths are provided for the surround and auxiliary channels which allow the user to bypass the high pass filtering operation and apply the unfiltered signals directly to the analogue volume controls. register address bit label default description 0 auxlbyp 0 bypass select for aux left output 0 = bass managed 1 = bypass 1 auxrbyp 0 bypass select for aux right output 0 = bass managed 1 = bypass 2 surlbyp 0 bypass select for surround left output 0 = bass managed 1 = bypass (27h) bass management bypass 3 surrbyp 0 bypass select for surround right output 0 = bass managed 1 = bypass table 7 bass management bypass register headphone output a stereo headphone output is provided which may be used to buffer out either the front l/r channels, or the aux l/r channels as required. control is via the hpsel bit. an independent volume control is provided for this output. register address bit label default description (25h) centre mixer control 1 6 hpsel 0 controls headphone output mux:- 0 = front l/r output on headphone channels 1 = aux l/r output on headphone channels table 8 headphone source select
pre-production wm8777 w pp rev 3.0 january 2005 21 output powerdown the analogue output signal paths are all disabled by default and can be controlled by writing to the appropriate software control register. register address bit label default description 0 auxlpd 1 auxiliary left output powerdown. 0 = enabled 1 = disabled 1 auxrpd 1 auxiliary right output powerdown. 0 = enabled 1 = disabled 2 surlpd 1 surround left output powerdown. 0 = enabled 1 = disabled 3 surrpd 1 surround right output powerdown. 0 = enabled 1 = disabled 4 lfepd 1 lfe output powerdown. 0 = enabled 1 = disabled 5 ctrpd 1 center output powerdown. 0 = enabled 1 = disabled 6 frtlpd 1 front left output powerdown. 0 = enabled 1 = disabled 7 frtrpd 1 front right output powerdown. 0 = enabled 1 = disabled (2dh) output powerdown 8 hppd 1 headphone output powerdown. 0 = enabled 1 = disabled table 9 output powerdown register
wm8777 pre-production w pp rev 3.0 january 2004 22 digital audio interface routing options the wm8777 has extremely flexible digital audio interface routing options which are illustrated in figure 4. it has an s/pdif receiver, s/pdif transmitter and two digital audio interfaces. each dac has its own digital input pin pdataip1/2/3/4. internal multiplexors in the primary audio interface (dac) allow the data received on any din pin to be routed to any dac .any din pin routed to dac1 is also routed to the s/pdif and secondary audio interface transmitters. dac1 may also be used to convert received s/pdif data to analogue, while dacs 2-4 take data only from the primary audio interface. the primary audio interface can output adc data, received s/pdif data or data from the secondary audio interface on the pdataop pin. the secondary audio interface can output adc data, received s/pdif data and data received through pdataip1-4 on the sdataop pin. the s/pdif transmitter can output s/pdif received data, and converts adc data and data from both audio interfaces into s/pdif format and outputs them on spdifop. figure 4 wm8777 digital routing diagram
pre-production wm8777 w pp rev 3.0 january 2005 23 register address bit label default description 0 rx2dac 0 received s/pdif pcm data to dac. 0 = dac1 takes data from primary audio interface. 1 = dac1 takes data from s/pdif receiver. note: if dacs 2, 3 and 4 are disabled, dac1 uses the subframe rate of the s/pdif input with respect to any selected mclk. pll clock should be selected to set the f s mode. if dac 2, 3 or 4 are enabled, the user must ensure that daclrc and the s/pdif subframe are operating at the same rate; any difference will cause a sample slip on dac1. 2:1 txsrc[1:0] 00 s/pdif transmitter data source. 00 = s/pdif received data. 01 = adc digital output data. 10 = secondary audio interface received data 11 = dac audio interface received data. note: the output rate is determined by the source of the data to be transmitted. the adc outputs s/pdif at a rate determined by lrclk. 5:4 paifsrc[1:0] 01 audio interface output source 00 = s/pdif received data 01 = adc digital output data 10 = secondary audio interface received data 11 = power-down primary audio interface transmitter note: for cases 00 and 10, the user must ensure that the source rate matches the transmit rate; any difference will cause samples to be lost. for optimum performance, the paif should be operated in master mode, with the master clock source the same as the paif source. r65 (41h) interface source select 7:6 saifsrc[1:0] 00 secondary audio interface transmitter data source. 00 = s/pdif received data. 01 = adc digital output data. 10 = power-down secondary audio interface transmitter 11 = primary audio interface received data. note: for cases 00 and 11, the user must ensure that the source rate matches the transmit rate; any difference will cause samples to be lost. for case 01, if paifsrc is not also 01, the adc operation rate is set by the slrc and adcclksrc/pll2adc register bits. table 10 interface output selection register
wm8777 pre-production w pp rev 3.0 january 2004 24 control interface operation the wm8777 is controlled using a 2-wire (plus readback pin) or 3-wire (plus readback pin) spi compatible serial interface. the interface configuration is determined by the state of the gpio/mode pin on power up. if the gpio/mode pin is low while the power on reset is being applied internally, the 2-wire configuration is selected. if gpio/mode is high while the power on reset is being applied internally, the 3-wire configuration is selected - see table 11. the control interface is 5v tolerant, meaning that the control interface input signals csb, sclk and sdin may have an input high level of 5v while dvdd is 3v. input thresholds are determined by dvdd. gpio/mode at power up control low 2-wire high 3-wire table 11 control interface selection 3-wire (spi compatible) serial control mode with additional readback pin sdin is used for the program data, sclk is used to clock in the program data and csb is used to latch the program data. sdin is sampled on the rising edge of sclk. the 2-wire interface protocol with readback is shown in figure 5 . figure 5 3 wire spi compatible interface 1. b[15:9] are control address bits 2. b[8:0] are control data bits 3. csb is edge sensitive C the data is latched on the rising edge of csb. 3-wire register readback the read-only registers in the s/pdif section can be read back via the sdout pin. to enable readback the readen3 bit must be set. register address bit label default description 4 readen3 0 3-wire read-back mode enable. 0 = 3-wire read-back mode disabled 1 = 3-wire read-back mode enabled (4ah) read-back control 5 readen2 0 2-wire read-back mode enable. 0 = 2-wire read-back mode disabled 1 = 2-wire read-back mode enabled table 12 readback control register the 3-wire interface readback protocol is shown in figure 6. note that the sdout pin is tri-state unless csb is held low, therefore csb must be held low for the duration of the read.
pre-production wm8777 w pp rev 3.0 january 2005 25 figure 6 3-wire spi compatible control interface readback 2-wire serial control mode with additional readback pin the wm8777 supports software control via a 2-wire (plus readback pin) serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the wm8777). the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8777, the wm8777 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised, the wm8777 returns to the idle condition and wait for a new start condition and valid address. once the wm8777 has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the wm8777 register address plus the first bit of register data). the wm8777 then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8777 acknowledges again by pulling sdin low. the transfer of data is complete when there is a low to high transition on sdin while sclk is high. after receiving a complete address and data sequence the wm8777 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. figure 7 2-wire serial control interface the wm8777 has two possible device addresses, which can be selected using the csbpin. csbstate device address in 2- wire mode low or unconnected 0011010 high 0011011 table 13 2-wire mpu interface address selection sdin sclk address wr ack b15-b8 ack b7-b0 ack device address [wr=0] in stop start out out out in in register address and 1st data bit remaining data bits
wm8777 pre-production w pp rev 3.0 january 2004 26 2-wire serial readback the wm8777 allows readback of certain registers in 2-wire mode, with data output on the sdout pin. readback is set by writing to the readback control register (see table 12) to set readen2 to 1. figure 8 2-wire readback
pre-production wm8777 w pp rev 3.0 january 2005 27 control interface timing C 3-wire mode figure 9 spi compatible control interface input timing test conditions dvdd = 3.3v, agnd = 0v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, adc/dac in slave mode unless otherwise stated. parameter symbol min typ max unit sclk rising edge to csbrising edge t scs 60 ns sclk pulse cycle time t scy 80 ns sclk pulse width low t scl 30 ns sclk pulse width high t sch 30 ns sdin to sclk set-up time t dsu 20 ns sclk to sdin hold time t dho 20 ns csb pulse width low t csl 20 ns csb pulse width high t csh 20 ns csb rising to sclk rising t css 20 ns table 14 sclk timing requirements
wm8777 pre-production w pp rev 3.0 january 2004 28 control interface timing C 2-wire mode figure 10 control interface timing C 2-wire serial control mode (mode=0) test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated parameter symbol min typ max unit program register input information sclk frequency 0 400 khz sclk low pulse-width t 1 600 ns sclk high pulse-width t 2 1.3 us hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns table 15 2-wire control interface timing information t 3 t 1 t 6 t 9 t 2 t 5 t 7 t 3 t 4 t 8 sdin sclk
pre-production wm8777 w pp rev 3.0 january 2005 29 master clock in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio systems master clock. the external master system clock can be applied directly through the mclk input pin with no software configuration necessary. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the adc and dac. master clock timing figure 11 master clock timing requirements test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, adc/dac in slave mode unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information mclk system clock pulse width high t mclkh 11 ns mclk system clock pulse width low t mclkl 11 ns mclk system clock cycle time t mclkp 28 ns mclk duty cycle 40:60 60:40 table 16 master clock timing requirements the master clock for wm8777 supports dac and adc audio sampling rates from 128fs to 1152fs, where fs is the audio sampling frequency (pdataiplrc or pdataoplrc) typically 32khz, 44.1khz, 48khz, 96khz, or 192khz. the master clock is used to operate the digital filters and the noise shaping circuits. the wm8777 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clo cks). if there is a greater than 32 clocks error the interface sets itself to the highest rate available, 1152fs. the master clock must be synchronised with pdataoplrc/pdataiplrc, although the wm8777 is tolerant of phase variations or jitter on this clock. t mclkl t mclkh t mclkp mclk
wm8777 pre-production w pp rev 3.0 january 2004 30 audio sampling rates and audio interfaces digital audio interfaces the wm8777 has two audio interfaces C a primary audio interface and a secondary audio interface. the primary audio interface has four data inputs (pdataip1/2/3/4), one data output (pdataop), and is controlled by pbclk, pdataoplrc and pdataiplrc clock pins. the secondary audio interface has one input (sdataip), one output (sdataop) and is controlled by sbclk and slrc clock pins. both audio interfaces operate in either slave or master mode, selectable using the paifrx_ms and sms control bits. in both master and slave modes pdataip1/2/3/4 and sdataip are always inputs to the wm8777 and pdataop and sdataop are always outputs. the default is slave mode. slave mode in slave mode (paifrx_ms/sms=0) pdataoplrc, pdataiplrc, slrc, pbclk and sbclk are inputs to the wm8777. pdataip1/2/3/4, pdataoplrc and pdataiplrc are sampled by the wm8777 on the rising edge of pbclk. sdataip and slrc are sampled by the wm8777 on the rising edge of sbclk. data output pdataop changes on the falling edge of pbclk and data output on sdataop changes on the falling edge of sbclk. by setting control bit paifrx_bcp the polarity of pbclk may be reversed so that pdataip1/2/3/4, pdataoplrc and pdataiplrc are sampled on the falling edge of pbclk and pdataop changes on the rising edge of pbclk. similarly the polarity of sbclk can be reversed using control bit sbcp. figure 12 digital audio interface C slave mode figure 13 digital audio data timing C slave mode
pre-production wm8777 w pp rev 3.0 january 2005 31 test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, adc/dac in slave mode unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information pbclk cycle time t bcy 50 ns pbclk pulse width high t bch 20 ns pbclk pulse width low t bcl 20 ns pdataiplrc/pdataopl rc set-up time to pbclk rising edge t lrsu 10 ns pdataiplrc/pdataopl rc hold time from pbclk rising edge t lrh 10 ns pdataip1/2/3/4 set-up time to pbclk rising edge t ds 10 ns pdataip1/2/3/4 hold time from pbclk rising edge t dh 10 ns pdataop propagation delay from pbclk falling edge t dd 0 10 ns table 17 digital audio data timing C slave mode note : pdataoplrc and pdataiplrc should be synchronous with mclk, although the wm8777 interface is tolerant of phase variations or jitter on these signals. the dacs support system clock to sampling clock ratios of 256fs to 1152fs when the dac signal processing of the wm8777 is programmed to operate at 128 times oversampling rate (dacosr=0). the dacs support ratios of 128fs and 192fs when the wm8777 is programmed to operate at 64 times oversampling rate (dacosr=1). the adc supports system clock to sampling clock ratios of 128fs to 1152fs. the signal processing for the wm8777 adc typically operates at an oversampling rate of 128fs. for adc operation at 96khz in 256fs or 384fs mode it is recommended that the user set the adcosr bit. this changes the adc signal processing oversample rate from 128fs to 64fs. for adc operation at 192khz in 128fs or 192fs mode it is recommended that the user set the adcosr bit. this changes the adc signal processing oversample rate from 64fs to 32fs. table 18 shows the typical system clock frequencies for adc operation at both 128 times oversampling rate (adcosr=0) and 64 times oversampling rate (adcosr=1), and dac operation at 128 times oversampling rate (dacosr=0). table 19 shows typical system clock frequencies for adc operation at 32/64 times oversampling rate (adcosr=1), and dac operation at 64 times oversampling rate (dacosr =1). system clock frequency (mhz) sampling rate (pdataiplrc/ pdataoplrc) 256fs 384fs 512fs 768fs 1152fs 32khz 8.192 12.288 16.384 24.576 36.864 44.1khz 11.2896 16.9340 22.5792 33.8688 unavailable 48khz 12.288 18.432 24.576 36.864 unavailable 96khz 24.576 36.864 unavailable unavailable unavailable table 18 adc and dac system clock frequencies versus sampling rate. (adc operation at either 128 times oversampling rate (adcosr=0) or 64 times oversampling rate (adcosr=1), dac operation at 128 times oversampling rate, dacosr=0)
wm8777 pre-production w pp rev 3.0 january 2004 32 system clock frequency (mhz) sampling rate (pdataiplrc/ pdataoplrc) 128fs 192fs 96khz 12.288 18.432 192khz 24.576 36.864 table 19 adc and dac system clock frequencies versus sampling rate. (adc operation at 32/64 times oversampling rate (adcosr=1), dac operation at 64 times oversampling rate (dacosr=1) master mode in master mode pbclk, pdataiplrc, pdataoplrc, slrc and sbclk are generated by the wm8777. figure 14 audio interface - master mode the frequencies of pdataoplrc, pdataiplrc and slrc are set by setting the required ratio of mclk to pdataiplrc, pdataoplrc and slrc using the paifrx_rate, paiftx_rate and saifrate control bits respectively, see table 20. paiftx_rate[2:0]/ paifrx_rate[2:0] mclk : pdataoplrc/pdataiplr c/slrc ratio 000 128fs 001 192fs 010 256fs 011 384fs 100 512fs 101 768fs 110 1152fs table 20 master mode mclk:lrclk ratio select table 21 shows the settings for paiftx_rate, paifrx_rate and saifrate for common sample rates and mclk frequencies.
pre-production wm8777 w pp rev 3.0 january 2005 33 system clock frequency (mhz) 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling rate (pdataiplrc/ pdataoplrc) paiftx_rate/ paifrx_rate/ saifrate =000 paiftx_rate/ paifrx_rate/ saifrate =001 paiftx_rate/ paifrx_rate/ saifrate =010 paiftx_rate/ paifrx_rate/ saifrate =011 paiftx_rate/ paifrx_rate/ saifrate =100 paiftx_rate/ paifrx_rate/ saifrate =101 paiftx_rate/ paifrx_rate/ saifrate =110 32khz 4.096 6.144 8.192 12.288 16.384 24.576 36.864 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 unavailable 48khz 6.144 9.216 12.288 18.432 24.576 36.864 unavailable 96khz 12.288 18.432 24.576 36.864 unavailable unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable unavailable table 21 master mode adc/pdataiplrc frequency selection pbclk is also generated by the wm8777. the frequency of pbclk depends on the mode of operation. in 128/192fs modes (paiftx_rate/paifrx_rate=000 or 001) pbclk = mclk/2. in 256/384/512/768/1152fs modes (paiftx_rate/paifrx_rate=010 or 011 or 100 or 101 or 110) pbclk = mclk/4. however if dsp mode is selected as the audio interface mode then pbclk=mclk. this is to ensure that there are sufficient pbclks to clock in all eight channels. note that dsp mode cannot be used in 128fs mode for word lengths greater than 16-bits or in 192fs mode for word lengths greater than 24 bits. figure 15 digital audio data timing C master mode test conditions dvdd = 3.3v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, adc/dac in slave mode unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information pdataoplrc/pdataipl rc propagation delay from pbclk falling edge t dl 0 10 ns pdataop propagation delay from pbclk falling edge t dda 0 10 ns pdataip1/2/3/4 setup time to pbclk rising edge t dst 10 ns pdataip1/2/3/4 hold time from pbclk rising edge t dht 10 ns table 22 digital audio data timing C master mode
wm8777 pre-production w pp rev 3.0 january 2004 34 master mode registers control bit paifrx_ms selects between primary audio interface master and slave modes. control bit sms selects between secondary audio interface master and slave modes. register address bit label default description 7 paiftx_ms 0 master/slave interface mode select. if adcclksrc is set high then this register control whether the adc clocks are in master or slave mode/ 0 = slave mode C pdataoplrc and adcpbclk are inputs 1 = master mode C pdataoplrc and adcpbclk are outputs (19h) master mode control 8 paifrx_ms 0 maser/slave interface mode select 0 = slave mode C pdataoplrc, pdataiplrc and pbclk are inputs 1 = master mode C pdataoplrc, pdataiplrc and pbclk are outputs note if adcclksrc is set high then this register only controls pdataiplrc and pbclk. (3fh) secondary interface master mode control 3 sms 0 master/slave interface mode select 0 = slave mode C slrc and sbclk are inputs 1 = master mode C slrc and sbclk are outputs table 23 master mode registers in master mode the wm8777 generates pdataoplrc, pdataiplrc and pbclk. these clo cks are derived from master clock and the ratio of mclk to pdataoplrc and pdataiplrc are set by paiftx_rate, paifrx_rate and saifrate. register address bit label default description 2:0 paiftx_rate [2:0] 010 (19h) master mode control 6:4 paifrx_rate [2:0] 010 (3fh) secondary interface master mode control 2:0 saifrate [2:0] 010 master mode mclk:lrclk ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs (3fh) secondary interface 5:4 saifclksrc[1:0] 00 audio interface master clock source when sms is 1. 00 = mclk 01 = gpio (if a dcclksrc is set) 10 = pll clock 11 = pll clock table 24 master mode mclk:lrclk regsiters
pre-production wm8777 w pp rev 3.0 january 2005 35 audio interface formats audio data is applied to the wm8777 via the primary and secondary audio interface. five popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp early mode ? dsp late mode all five formats send the msb first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. audio data for each stereo channel is time multiplexed with the interfaces left-right-clock (pdataoplrc/pdataiplrc), indicating whether the left or right channel is present. the pdataoplrc/pdataiplrc is also used as a timing reference to indicate the beginning or end of the data words. in left justified, right justified and i 2 s modes, the minimum number of pbclks per lrclk period is 2 times the selected word length. lrclk must be high for a minimum of word length pbclks and low for a minimum of word length pbclks. any mark to space ratio on lrclk is acceptable provided the above requirements are met. the primary audio interface has left-right-clo cks pdataoplrc and pdataiplrc, and bit-clock pbclk. the secondary audio interface has left-right-clock slrc, and bit-clock sbclk. in dsp early or dsp late mode, all 8 dac channels are time multiplexed onto pdataip1. pdataiplrc is used as a frame sync signal to identify the msb of the first word. the minimum number of pbclks per pdataiplrc period is 8 times the selected word length. any mark to space ratio is acceptable on pdataiplrc provided the rising edge is correctly positioned. the adc data may also be output in dsp early or late modes, with pdataoplrc used as a frame sync to identify the msb of the first word. the minimum number of pbclks per pdataoplrc period is 2 times the selected word length. the secondary audio interface also supports dsp modes with slrc used as a frame sync and data input on sdataip, and data output on sdataop. the minimum number of sbclks per slrc period is 2 times the selected word length. left justified mode in left justified mode, the msb of the input data (pdataip/sdataip) is sampled by the wm8777 on the first rising edge of pbclk/sbclk following a lrclk transition. the msb of the output data (pdataop/sdataop) changes on the same falling edge of pbclk as slrc, and may be sampled on the next rising edge of pbclk. lrclks are high during the left samples and low during the right samples. figure 16 left justified mode timing diagram
wm8777 pre-production w pp rev 3.0 january 2004 36 right justified mode in right justified mode, the lsb of the input data (pdataip/sdataip) is sampled by the wm8777 on the rising edge of pbclk/sbclk preceding a lrclk transition. the lsb of the output data (pdataop/sdatop) changes on the falling edge of pbclk preceding a lrclk transition, and may be sampled on the nect rising edge of pbclk. lrclks are high during the left samples and low during the right samples (figure 17). figure 17 right justified mode timing diagram i 2 s mode in i 2 s mode, the msb of the input data is sampled by the wm8777 on the second rising edge of pbclk/sbclk following a lrclk transition. the msb of the output data changes on the first falling edge of pbclk following an lrclk transition, and may be sampled on the next rising edge of pbclk. lrcks are low during the left samples and high during the right samples. figure 18 i 2 s mode timing diagram dsp early mode in dsp early mode, the msb of dac channel 1 left data is sampled by the wm8777 on the second rising edge on pbclk following a pdataiplrc rising edge. dac channel 1 right and dac channels 2, 3 and 4 data follow dac channel 1 left data (figure 19). figure 19 dsp early mode timing diagram C dac data input
pre-production wm8777 w pp rev 3.0 january 2005 37 the msb of the left channel adc data is output on pdataop and changes on the first falling edge of pbclk following a low to high pdataoplrc transition and may be sampled on the rising edge of pbclk. the right channel adc data is contiguous with the left channel data (figure 20). figure 20 dsp early mode timing diagram C adc data output dsp late mode in dsp late mode, the msb of dac channel 1 left data is sampled by the wm8777 on the first pbclk rising edge following a pdataiplrc rising edge. dac channel 1 right and dac channels 2, 3 and 4 data follow dac channel 1 left data (figure 21). figure 21 dsp late mode timing diagram C dac data input the msb of the left channel adc data is output on pdataop and changes on the same falling edge of pbclk as the low to high pdataoplrc transition and may be sampled on the rising edge of pbclk. the right channel adc data is contiguous with the left channel data (figure 22). figure 22 dsp late mode timing diagram C adc data output in both early and late dsp modes, dacl1 is always sent first, followed immediately by dacr1 and the data words for the other 6 channels. no pbclk edges are allowed between the data words. the word order is dac1 left, dac1 right, dac2 left, dac2 right, dac3 left, dac3 right, dac4 left, dac4 right. for dsp modes the secondary audio interface exhibits similar timing to the adc where data is input on sdataip, and output on sdataop.
wm8777 pre-production w pp rev 3.0 january 2004 38 digital audio interface control registers interface format for primary and secondary interfaces are selected via the paifrx_fmt register bits: register address bit label default description (18h) primary interface control (rx) 1:0 paifrx_fmt [1:0] 10 (1bh) primary interface control (tx) 1:0 paiftx_fmt [1:0] 10 (3eh) secondary interface control 1:0 saif_fmt [1:0] 10 interface format select 00 = right justified mode 01 = left justified mode 10 = i 2 s mode 11 = dsp (early or late) mode table 25 format registers in left justified, right justified or i 2 s modes, the paifrx_lrp register bit controls the polarity of pdataiplrc/pdataoplrc/slrc. if this bit is set high, the expected polarity of pdataiplrc/pdataoplrc/slrc will be the opposite of that shown in figure 16, figure 17 and figure 18. note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. in dsp modes, the paifrx_lrp register bit is used to select between early and late modes. register address bit label default description (18h) primary interface control (rx) 2 paifrx_lrp 0 (1bh) primary interface control (tx) 2 paiftx_lrp 0 (3eh) secondary interface control 2 saif_lrp 0 in left/right/i 2 s modes: pdataoplrc/pdataiplrc/slrc polarity (normal) 0 = normal lrclk polarity 1 = inverted lrclk polarity in dsp mode: 0 = early dsp mode 1 = late dsp mode table 26 lrclk polarity registers by default, pdataiplrc, pdataoplrc, slrc, pdataip1/2/3/4 and sdataip are sampled on the rising edge of pbclk/sbclk and should ideally change on the falling edge. data sources that change pdataiplrc, pdataoplrc, slrc, pdataip1/2/3/4 and sdataop on the rising edge of pbclk/sbclk can be supported by setting the paifrx_bcp register bit. setting paifrx_bcp to 1 inverts the polarity of pbclk/sbclk to the inverse of that shown in figure 19, figure 20, figure 21 and figure 22. register address bit label default description (18h) primary interface control (rx) 3 paifrx_bcp 0 (1bh) primary interface control (tx) 3 paiftx_bcp 0 (3eh) secondary interface control 3 saif_bcp 0 pbclk/sbclk polarity (dsp modes) 0 = normal pbclk polarity 1 = inverted pbclk polarity table 27 pbclk polarity registers the paifrx_wl[1:0] bits are used to control the input word length. note: if 32-bit mode is selected in right justified mode, the wm8777 defaults to 24 bits.
pre-production wm8777 w pp rev 3.0 january 2005 39 register address bit label default description (18h) primary interface control (rx) 5:4 paifrx_wl[1:0] 10 (1bh) primary interface control (tx) 5:4 paiftx_wl [1:0] 10 (3eh) secondary interface control 5:4 saif_wl [1:0] 10 input word length 00 = 16 bit data 01 = 20 bit data 10 = 24 bit data 11 = 32 bit data table 28 word length registers in all modes, the data is signed 2's complement. the digital filters always input 24-bit data. if the dac is programmed to receive 16 or 20 bit data, the wm8777 pads the unused lsbs with zeros. if the dac is programmed into 32 bit mode, the 8 lsbs are ignored. note: in 24 bit i 2 s mode, any width of 24 bits or less is supported provided that lrclk is high for a minimum of 24 pbclks and low for a minimum of 24 pbclks. if exactly 32 bit clo cks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode. powerdown modes the wm8777 has powerdown control bits allowing specific parts of the wm8777 to be powered down when not in use. the 6-channel input source selector and input buffer may be powered down using control bit ainpd. when ainpd is set all inputs to the source selector (ain1l/r to ain6l/r) are switched to a buffered vmidadc and the adc is also powered off. the control bit adcpo powers off the adc. the four stereo dacs each have a separate powerdown control bit, dacpd[3:0] allowing individual stereo dacs to be powered down when not in use. the analogue output mixers and pgas may also be powered down by setting outpd1/2/3/4. outpd1/2/3/4 also switch the analogue outputs voutl/r to vmiddac to maintain a dc level on the output. spdiftxd and spdifrxd will powerdown the s/pdif transmitter and receiver. setting all of ainpd, adcpd, dacpd[3:0], spdiftxd, spdifrxd and outpd[3:0] will powerdown everything except the references vmidadc, adcref and vmiddac. these may be powered down by setting pdwn. setting pdwn will override all other powerdown control bits. it is recommended that the 6-channel input mux and buffer, adc, dac and output mixers and pgas are powered down before setting pdwn. the default is for all powerdown bits to be set except pdwn. register address bit label default description 0 pwdn 0 chip powerdown control (works in tandem with the other powerdown registers): 0 = all digital circuits running, outputs are active 1 = all digital circuits in power save mode, outputs muted 1 adcpd 1 adc powerdown: 0 = adc enabled 1 = adc disabled 5:2 dacpd[3:0] 1111 dac powerdowns (0 = dac enabled, 1 = dac disabled) dacpd[0] = dac1 dacpd[1] = dac2 dacpd[2] = dac3 dacpd[3] = dac4 6 spdiftxd 1 spdif_tx powerdown 0 = spdif_tx enabled 1 = spdif_tx disabled (1ah) powerdown control 7 spdifrxd 1 spdif_rx powerdown 0 = spdif_rx enabled 1 = spdif_rx disabled
wm8777 pre-production w pp rev 3.0 january 2004 40 8 oscpd 1 osc power down 0 = oscillator enabled 1 = oscillator disabled (31h) adc mux and buffer powerdown control 8 ainpd 1 input mux and buffer powerdown 0 = input mux and buffer enabled 1 = input mux and buffer powered down 7 outpd1 1 mixer powerdown select 0 = powerup 1 = powerdown (32h) output mux and powerdown control 1 8 outpd2 1 mixer powerdown select 0 = powerup 1 = powerdown 7 outpd3 1 mixer powerdown select 0 = powerup 1 = powerdown (33h) output mux and powerdown control 2 8 outpd4 1 mixer powerdown select 0 = powerup 1 = powerdown (37h) pll control 4 0 pllpd 1 0 = enable pll 1 = disable pll 0 auxlpd 1 auxiliary left output powerdown. 0 = enabled 1 = disabled 1 auxrpd 1 auxiliary left output powerdown. 0 = enabled 1 = disabled 2 surlpd 1 surround left output powerdown. 0 = enabled 1 = disabled 3 surrpd 1 surround right output powerdown. 0 = enabled 1 = disabled 4 lfepd 1 lfe output powerdown. 0 = enabled 1 = disabled 5 ctrpd 1 center output powerdown. 0 = enabled 1 = disabled 6 frtlpd 1 front left output powerdown. 0 = enabled 1 = disabled 7 frtrpd 1 front right output powerdown. 0 = enabled 1 = disabled (2dh) output powerdown 8 hppd 1 headphone output powerdown. 0 = enabled 1 = disabled
pre-production wm8777 w pp rev 3.0 january 2005 41 5:4 paifsrc [1:0] 01 audio interface output source 00 = s/pdif received data 01 = adc digital output data 10 = secondary audio interface received data 11 = power-down primary audio interface transmitter r65 (41h) interface source select 7:6 saifsrc [1:0] 00 secondary audio interface transmitter data source. 00 = s/pdif received data. 01 = adc digital output data. 10 = power-down secondary audio interface transmitter 11 = primary audio interface received data. table 29 powerdown registers
wm8777 pre-production w pp rev 3.0 january 2004 42 master clock and phase locked loop the wm8777 has an on-chip phase-locked loop (pll) circuit that can be used to: ? generate master clo cks for the wm8777 audio functions from another external clock. ? generate a clock for another part of the system from an existing audio master clock. figure 23 pll and clock select circuit the pll frequency ratio r = f 2 /f 1 (see figure 23 ) can be set using k and n (see : n = int r k = int (2 22 (r-n)) the pll circuit is made up of an analogue pll (pll1) and a digital pll (pll2). n and k values can be set manually for the analogue pll (pll1). the s/pdif receiver monitors the input data stream and constantly varies the n and k values on pll2 to maintain a stable recovered clock frequency. in order for the s/pdif receiver to automatically lock to input s/pdif signal frequencies of 32khz, 44.1khz and 48khz, f 2 of pll1 (see figure 23) must be in the range of 94.6118mhz. this gives the s/pdif receiver the maximum pulling range to lock onto the incoming data stream. example: mclk=12mhz, required clock = 12.288mhz. r should be chosen to ensure 5 < n < 13. there is a divide by 4 and a selectable divide by 2 after the pll which should be set to meet this requirement. enabling the divide by 2 sets the required f 2 = 8 x 12.288mhz = 98.304mhz. r = 98.304 / 12 = 8.192 n = int r = 8 k = int ( 2 22 x (8.192 C 8)) = 805306 = c49bah
pre-production wm8777 w pp rev 3.0 january 2005 43 s/pdif data/clock recovery the wm8777 uses a patented clock and data recovery scheme that allows an extremely low jitter bandwidth on the output recovered clock. this is done by isolating the clock and data recovery systems. the data is recovered and stored in a buffer which modifies the frequency of the recovered clock via a filter. this filter controls the jitter bandwidth using the register value fpll. data recovery buffer filter clock recovery spdif in fpll spdif out clock out figure 24 s/pdif data and clock recovery system the jitter bandwidth affects the rate at which the clock can change to track the incoming data rate, resulting in a slower tracking time as fpll is increased. note that this effect is only apparent on slowly changing input frequencies. input signals that change frequency by a significant amount, i.e. data rate changes, will cause the system to lose lock and to enter a quick tracking mode which will open the filter bandwidth out to the maximum. table 30 lists the cut-off frequencies for the different values of fpll. register address bit label default description (42h) s/pdif data/clock recovery 5:3 fpll[2:0] 111 -3db lpf cut-off 000 = invalid 001 = 28.84hz 010 = 14.92hz 011 = 7.46hz 100 = 3.73hz 101 = 1.87hz 110 = 0.97hz 111 = 0.47hz table 30 pll frequency ratio control
wm8777 pre-production w pp rev 3.0 january 2004 44 register address bit label default description 6 mclkopen 0 mclk pin output enable 0 = mclk pin is an input 1 = mclk pin is an output (refer to mclkoutsrc below (18h) primary interface control (rx) 7 mclkoutsrc 0 mclk pin output source 0 = pll 1 = crystal clock output. (34h) pll control 1 8:0 pll_k[8:0] 121 (hex) (35h) pll control 2 8:0 pll_k[17:9] 17e (hex) 3:0 pll_k[21:18] d(hex) fractional (k) part of pll input/output frequency ratio (treat as one 22-digit binary number). 4 clkoutsrc 0 clkout pin source:- 0 = pll clock output 1 = crystal clock output. 6 pll2dac 0 dac clock source 0 = mclk pin 1 = pll clock 7 pll2adc 0 adc clock source 0 = mclk or adcmlck pin 1 = pll clock (36h) pll control 3 8 pll2tx 1 s/pdif tx clock source 0 = mlck or adcmclk pin 1 = pll clock 0 pllpd 1 0 = enable pll 1 = disable pll 1 postscale 0 0 = no post scale 1= divide pll by 2 after pll 2 frac_en 0 0 = integer n only pll 1 = integer n and fractional k pll 3 prescale 0 0 = no pre-scale 1 = divide mclk by 2 prior to pll (37h) pll control 4 8:4 pll_n[4:0] 00000 integer (n) divisor part of pll input/output frequency ratio. use values greater than 5 and less than 13. (40h) s/pdif receiver input selector 8 adcclksrc 0 adc clock source 0 = adcmclk is from mclk pin and adcpbclk is from pbclk pin. 1 = adcmclk is from gpio1, and adcpbclk is from gpio2.(note that when in this mode rxinsel must not be set to 01 or 10) table 31 pll frequency ratio control note: mclkopen should not be toggled if any part of the wm8777 is actively using mclk as its clock source.
pre-production wm8777 w pp rev 3.0 january 2005 45 the pll performs best when f 2 is around 90mhz. its stability peaks at n=8. some example settings are shown below. xtalc lk (mhz) (f1) desired output (mhz) f2 (mhz) pre scale post scale r n (hex) k (hex) 11.91 11.2896 90.3168 0 1 7.5833 7 25545c 11.91 12.288 98.304 0 1 8.2539 8 103ff6 12 11.2896 90.3168 0 1 7.5264 7 21b089 12 12.288 98.304 0 1 8.192 8 c49ba 13 11.2896 90.3168 0 1 6.9474 6 3ca2f4 13 12.288 98.304 0 1 7.5618 7 23f548 14.4 11.2896 90.3168 0 1 6.272 6 116872 14.4 12.288 98.304 0 1 6.8267 6 34e818 19.2 11.2896 90.3168 1 1 9.408 9 1a1cac 19.2 12.288 98.304 1 1 10.24 a f5c28 19.68 11.2896 90.3168 1 1 9.1785 9 b6d22 19.68 12.288 98.304 1 1 9.9902 9 3f6017 19.8 11.2896 90.3168 1 1 9.1229 9 7ddca 19.8 12.288 98.304 1 1 9.9297 9 3b8023 24 11.2896 90.3168 1 1 7.5264 7 21b089 24 12.288 98.304 1 1 8.192 8 c49ba 26 11.2896 90.3168 1 1 6.9474 6 3ca2f4 26 12.288 98.304 1 1 7.5618 7 23f548 27 11.2896 90.3168 1 1 6.6901 6 2c2b30 27 12.288 98.304 1 1 7.2818 7 12089e table 32 pll frequency examples s/pdif transceiver features ? iec-60958 compatible with 32 to 96k frames/s support ? support for rx and tx of s/pdif data ? clock synthesis pll with reference clock input and low jitter output ? input mux with support for up to 4 s/pdif inputs ? register controlled channel status bit configuration ? register read-back of recovered channel status bits and error flags ? detection of non-audio data, sample rate, de-emphasis ? programmable gpo for error flags and frame status flags an iec-60958 compatible s/pdif transceiver is integrated into the wm8777. operation of the s/pdif function may be synchronous or asynchronous to the rest of the digital audio circuits. the receiver performs data and clock recovery, and sends recovered data either off the chip to an external dsp (via primary or secondary audio interfaces), or if the data is audio pcm, it can route the stereo recovered data to dac1. the recovered clock may be routed out of the chip onto a pin for external use, and may be used to clock the internal dac and adc circuits as required. the transmitter generates s/pdif frames where audio data may be sourced from the adc, s/pdif receiver, primary or secondary audio interfaces.
wm8777 pre-production w pp rev 3.0 january 2004 46 s/pdif format s/pdif is a serial, bi-phase-mark encoded data stream. an s/pdif frame consists of two sub- frames. each sub-frame is made up of: ? preamble C a synchronization pattern used to identify the start of a 192-frame block or sub- frame ? 4-bit auxiliary data (aux) C ordered lsb to msb ? 20-bit audio data (24-bit when combined with aux) C ordered lsb to msb ? validity bit C a 1 indicates invalid data in that sub-frame ? user bit C over 192-frames, this forms a user data block, ? channel bit C over 192-frames, this forms a channel status block ? parity bit C used to maintain even parity over the sub-frame(except the preamble) an s/pdif block consists of 192 frames. channel and user blo cks are incorporated within the 192- frame s/pdif block. for consumer mode (as in the wm8777) only the first 40-frames are used to make up the channel and user blo cks. figure 25 illustrates the s/pdif format. . . . . . . . . . frame 192 frame 1 subframe 1 subframe 2 sync preamble aux v u c p audio sample word 3 4 7 8 27 28 0 31 32 bit word figure 25 s/pdif format clock recovery and generation the circuit comprises data and clock recovery blo cks, and a clock synthesis function in the event of no s/pdif input. as an integral part of these functions, an accurate, stable, crystal derived master clock must be input to the wm8777. this clock may be generated using the wm8777 crystal oscillator circuit, by connecting a suitable crystal across the xin xop pins, or else may be applied as a digital input to the xin pin. this reference clock input may have any frequency from 10mhz up to 27mhz. when s/pdif signals are being received, the pll will recover the audio mclk at a rate of 256fs. in the event of no s/pdif input, the pll will continue to synthesise a 128 or 256fs audio clock. if desired the s/pdif input may be ignored and the pll instructed to synthesise any desired audio clock rate (depending upon sample rate). the ratio of this audio clock to the reference clock frequency is set by programming the required value over the serial interface. audio sample rates from 32khz to 96khz are supported both by the s/pdif transceiver and the clock synthesiser. the reference clock input should be low jitter, hence it is recommended that a crystal connected to wm8777 oscillator is used to generate the clock. in this condition very low jitter audio clo cks will be generated, and s/pdif in-coming clo cks will likewise be de-jittered. the wm 8777 crystal derived clock, or the pll derived audio clock, may then be supplied to external circuits as low jitter clock references as required.
pre-production wm8777 w pp rev 3.0 january 2005 47 s/pdif transmitter the s/pdif transmitter generates the s/pdif frames, and outputs on the spdifop pin. the audio data for the frame can be taken from one of four sources, selectable using the txsrc register. the transmitter can be powered down using the spdiftxd register bit. register address bit label default description 2:1 txsrc[1:0] 00 s/pdif transmitter data source. 00 = s/pdif received data. 01 = adc digital output data. 10 = secondary audio interface received data 11 = primary audio interface received data. (41h) interface source select 3 txrxthru 0 only used if txsrc==00. configures only the channel bit in the s/pdif frame. 0 = channel data equal to recovered channel data. 1 = channel data taken from channel status registers. (1ah) powerdown control 6 spdiftxd 1 spdif_tx powerdown 0 = spdif_tx enabled 1 = spdif_tx disabled table 33 s/pdif tx control the wm8777 also transmits the preamble and vucp bits (validity, user data, channel status and parity bits). validity bit set to 0 (to indicate valid data) C unless txsrc=00 (s/pdif receiver), where validity is set by the receiver. user data set to 0 as user data configuration is not supported in the wm8777 C if txsrc=00 (s/pdif receiver) user data is set by the receiver. channel status the channel status bits form a 192-frame block - transmitted at 1 bit per sub-frame. each sub-frame forms its own 192-frame block. the wm8777 is a consumer mode device and only the first 40 bits of the block are used. all data transmitted from the wm8777 is stereo, so the channel status data is duplicated for both channels. the only exception to this is the channel number bits (23:20) which can be changed to indicate if the channel is left or right in the stereo image. bits within this block can be configured by setting the channel bit control registers (see tables 28-32 ). if txsrc is the s/pdif receiver, the channel bits are transmitted with the same values recovered by the receiver C unless txrxthru is se t, in which case they are set by the registers. note that the wm8777 expects to receive channel status data in consumer format. the channel status bits are defined differently for professional mode. the definitions on the following page do not hold for professional mode. parity bit this bit maintains even parity for data as a means of basic error detection. it is generated by the transmitter.
wm8777 pre-production w pp rev 3.0 january 2004 48 register address bit label channel status bit default description 0 con/pro 0 0 0 = consumer mode 1 = professional mode (not supported by wm8777) 1 audio_n 1 0 0 = s/pdif transmitted data is audio pcm. 1 = s/pdif transmitted data is not audio pcm. 2 cpy_n 2 0 0 = transmitted data has copyright asserted. 1 = transmitted data has no copyright assertion. 5:3 preemph [2:0] 5:3 000 000 = data from audio interface has no pre- emphasis. 001 = data from audio interface has pre- emphasis. 010 = reserved (audio interface has pre- emphasis). 011 = reserved (audio interface has pre- emphasis). all other modes are reserved and should not be used. (39h) s/pdif transmitter channel bit control 1 7:6 chstmode [1:0] 7:6 00 s/pdif channel status bits. 00 = only valid mode for consumer applications. all other modes are reserved. table 34 s/pdif tx channel bit control 1 register address bit label channel status bit default description (3ah) s/pdif transmitter channel bit control 2 7:0 catcode [7:0] 15:8 00000000 category code. refer to s/pdif specification for details. 00h indicates general mode. table 35 s/pdif tx channel bit control 2 register address bit label channel status bit default description 3:0 srcnum [3:0] 19:16 0000 source number. no definitions are attached to data. see s/pdif specification for details. channel number for subframe 1 chnum1 channel status bits[23:20] 00 0000 = do not use channel number 01 0001 = send to left channel 10 0010 = send to right channel 5:4 chnum1[1:0] 23:20 00 11 0000 = do not use channel number channel number for subframe 2 chnum2 channel status bits[23:20] 00 0000 = do not use channel number 01 0001 = send to left channel 10 0010 = send to right channel (3bh) s/pdif transmitter channel bit control 3 7:6 chnum2[1:0] 00 11 0000 = do not use channel number table 36 s/pdif tx channel bit control 3
pre-production wm8777 w pp rev 3.0 january 2005 49 register address bit label channel status bit default description 3:0 freq[3:0] 27:24 0001 sampling frequency. see s/pdif specification for details. 0001 = sampling frequency not indicated. (3ch) s/pdif transmitter channel bit control 4 5:4 clkacu[1:0] 29:28 11 clock accuracy of generated clock. 00 = level ii 01 = level i 10 = level iii 11 = interface frame rate not matched to sampling frequency. table 37 s/pdif tx channel bit control 4 register address bit label channel status bit default description 0 maxpaifrx_wl 32 1 maximum audio sample word length 0 = 20 bits 1 = 24 bits audio sample word length. 000 = word length not indicated txpaifrx_ wl maxpaifr x_wl==1 maxpaifr x_wl==0 001 20 bits 16 bits 010 22 bits 18 bits 100 23 bits 19 bits 101 24 bits 20 bits 110 21 bits 17 bits 3:1 txpaifrx_wl [2:0] 35:33 101 all other combinations reserved (3dh) s/pdif transmitter channel bit control 5 7:4 orgsamp [3:0] 39:36 0000 original sampling frequency. see s/pdif specification for details. 0000 = original sampling frequency not indicated table 38 s/pdif tx channel bit control 5
wm8777 pre-production w pp rev 3.0 january 2004 50 s/pdif receiver input selector the s/pdif receiver has one dedicated input, spin. there are three other pins which can be configured as either s/pdif inputs or general purpose outputs (gpos). the four s/pdif inputs go into a 4:1 mux, allowing one input to go to the s/pdif receiver for decoding. the s/pdif receiver can be powered down using the spdifrxd register bit. table 39 s/pdif rx input selection register audio data handling the s/pdif receiver recovers the data and vucp bits from each sub-frame. if the s/pdif input data is in pcm format the data can be internally routed to the stereo data input of dac1. the wm8777 can detect when the data is not in pcm format and will automatically mute the dac. see non-audio detection for more detail. the received data can also be output over the audio interfaces in any of the data formats supported. this can be done while simultaneously using dac1 for playback. the received data may also be re- transmitted over spdifop. user data the wm8777 can output recovered user data received over the gpio pins. see table 48 for general purpose pin control. channel status data the channel status bits are recovered from the incoming data stream and are used to control various functions of the device. the recovered maxpaifrx_wl and paifrx_wl bits are used to truncate the recovered 24-bit audio word to so that only the appropriate numbers of bits are used by the other interfaces (except the s/pdif transmitter which always sees the full 24-bit recovered word). should the recovered deemph channel-bit be set, and dac1 is used for playback, the de-emphasis filter is activated for that dac. it is assumed that the channel status is stereo and hence only channel 1 data is read. the channel status data is stored in 5 read-only registers which can be read back over the serial interface (see serial interface readback ). when the channel status data has been recovered and stored in registers, the csud (channel status update) bit goes high to indicate that the registers are ready for readback. it will go low again when the first sub-frame of data from the next block is received. csud can be output to one of the gpio pins. register address bit label default description 0 spdinmode 0 selects the input circuit type for the s/pdif input 0 = normal cmos input 1 = comparator input. compatible with 200mv ac coupled consumer s/pdif input signals. (40h) s/pdif receiver input selector 5:4 rxinsel[1:0] 00 s/pdif receiver input mux select. note that the general purpose inputs must be configured using gpioxop to be either cmos or comparator inputs if selected by rxinsel. 00 = s/pdif_in1 01 = s/pdif_in2 (gpio1) 10 = s/pdif_in3 (gpio2) 11 = s/pdif_in4 (gpio3)
pre-production wm8777 w pp rev 3.0 january 2005 51 the register descriptions for the channel status bits are given below. note that the descriptions below refer to consumer mode. the wm8777 may give erroneous behaviour if professional format data is input. register address bit label channel status bit description 0 con/pro 0 0 = consumer mode 1 = professional mode the wm8777 is a consumer mode device. detection of professional mode may give erroneous behaviour. 1 audio_n 1 recovered s/pdif channel status bit 1. 0 = data word represents audio pcm samples. 1 = data word does not represent audio pcm samples. 2 cpy_n 2 0 = copyright is asserted for this data. 1 = copyright is not asserted for this data. 3 preemph 3 0 = recovered s/pdif data has no pre- emphasis. 1 = recovered s/pdif data has pre- emphasis. (4ch) s/pdif receiver channel status register 1 (read-only) 5:4 reserved 5:4 reserved for additional de-emphasis modes. table 40 s/pdif rx channel status register 1 register address bit label channel status bit description (4dh) s/pdif receiver channel status register 2 (read-only) 7:0 catcode [7:0] 15:8 category code. refer to s/pdif specification for details. 00h indicates general mode. table 41 s/pdif rx channel status register 2 register address bit label channel status bit description 3:0 srcnum [3:0] 19:16 indicates number of s/pdif source. (4eh) s/pdif receiver channel status register 3 (read-only) 7:4 chnum1[3:0] 23:20 channel number for channel 1. 0000 = take no account of channel number (channel 1 defaults to left dac) 0001 = channel 1 to left channel 0010 = channel 1 to right channel table 42 s/pdif rx channel status register 3
wm8777 pre-production w pp rev 3.0 january 2004 52 register address bit label channel status bit description 3:0 freq[3:0] 27:24 sampling frequency. see s/pdif specification for details. 0001 = sampling frequency not indicated. (4fh) s/pdif receiver channel status register 4 (read-only) 5:4 clkacu[1:0] 29:28 clock accuracy of received clock. 00 = level ii 01 = level i 10 = level iii 11 = interface frame rate not matched to sampling frequency. table 43 s/pdif rx channel status register 4 register address bit label channel status bit description 0 maxpaifrx_wl 32 maximum audio sample word length 0 = 20 bits 1 = 24 bits audio sample word length. 000: word length not indicated rxpaifrx_ wl maxpaifr x_wl==1 maxpaifr x_wl==0 001 20 bits 16 bits 010 22 bits 18 bits 100 23 bits 19 bits 101 24 bits 20 bits 110 21 bits 17 bits 3:1 rxpaifrx_wl [2:0] 35:33 all other combinations are reserved and may give erroneous operation. data will be truncated internally when these bits are set. (50h) s/pdif receiver channel status register 5 (read-only) 7:4 orgsamp [3:0] 39:36 original sampling frequency. see s/pdif specification for details. 0000 = original sampling frequency not indicated table 44 s/pdif rx channel status register 5
pre-production wm8777 w pp rev 3.0 january 2005 53 error handling several kinds of error can be reported when decoding the incoming data. the error bits are written to a read-only register which can be read back by the user over the serial interface. reading back this register will reset it. register address bit label default description 0 unlock 0 pll unlock signal. 0 = pll is locked to incoming s/pdif stream. 1 = pll is not locked to the incoming s/pdif stream. 1 validity 0 v bit from s/pdif input stream. 0 = data word is valid. 1 = data word is not valid. 2 parityerr 0 even parity check. 0 = no parity errors detected. 1 = parity error detected. 3 bip 0 biphase coding of s/pdif input stream. 0 = biphase coding is correct. 1 = biphase coding error detected. 4 audio_n 0 received channel status bit 1 has changed. 0 = normal running. 1 = change on audio_n. 5 pcm_n 0 pcm_n bit has changed 0 = normal running. 1 = change on pcm_n. 6 cpy_n 0 received channel status bit 2 has changed. 0 = normal running. 1 = change on cpy_n. (4bh) s/pdif receiver error register (read-only) 7 spdif_mode 0 s/pdif mode change. 0: normal running 1: change in s/pdif frequency mode detected. table 45 s/pdif rx error status register when an error is detected the int signal is set high. this is a logical or of the error bits which can be output to a gpio (gpio1 by default). error bits can be masked off by setting the mask register. if an error bit is masked off then that error will not be written to the error register and will not cause a change on int. unlock, validity, parity and bip generate an interrupt when they go from low to high. these bits are sticky, i.e. the interrupt will remain until the user reads back the register to clear it. audio_n, pcm_n, cpy_n and spdif_mode will generate an interrupt on any change in status. the user can then determine the status of these bits by reading back the s/pdif status register.
wm8777 pre-production w pp rev 3.0 january 2004 54 register address bit label default description 0 audio_n received channel status bit 1 0 = data word represents audio pcm samples. 1 = data word does not represent audio pcm samples. 1 pcm_n detects non-audio data from a 96-bit sync code, as defined in iec-61937. 0 = sync code not detected. 1 = sync code detected C received data is not audio pcm. 2 cpy_n recovered s/pdif channel status bit 2. 0 = copyright is asserted for this data. 1 = copyright is not asserted for this data. note this signal is inverted and will cause an interrupt on logic 0. (51h) s/pdif status register (read-only) 4:3 spdif_mode s/pdif frequency mode. 00: mode not supported 01: 88-96khz 10: 44-48khz 11: 32khz table 46 s/pdif rx status register should the incoming s/pdif sub-frame contain a parity error or a bip error, it is assumed the sub- frame has become corrupted. these errors would normally be flagged, but if the error bits have been masked, the wm8777 will instead overwrite the recovered frame (i.e. both sub-frames) with either all-zeros or the last data sample (depending on how fillmode has been set). when the flags are unmasked and an error is detected, the data is allowed to pass, albeit still corrupted. similarly, if validity is detected as 1, it is assumed the data within the s/pdif frame is invalid. if validity is masked, then data is overwritten depending on fillmode, else validity is flagged and the (invalid) data is allowed to pass. (note1: alwaysvalid must be set to 0, else the recovered validity bit will be ignored). (note 2: for the s/pdif receiver to s/pdif transmitter path, only masked validity errors will cause data to be overwritten C parity and bip errors have no effect). register address bit label default description (49h) s/pdif receiver error mask 7:0 mask[7:0] 0000000 when a lag is masked, it does not update the error register or contribute to the interrupt pulse. 0 = unmask, 1 = mask. mask[0] = mask control for unlock mask[1] = mask control for validity mask[2] = mask control for parityerr mask[3] = mask control for bip mask[4] = mask control for audio_n mask[5] = mask control for pcm_n mask[6] = mask control for cpy_n mask[7] = mask control for spdif_mode 6 fillmode 0 determines what spdif_rx should do if the validity bit indicates invalid data: 0 = data from spdif_rx remains static at last valid sample. 1 = data from spdif_rx is output as all zeros. (40h) s/pdif receiver input selector 7 alwaysvalid 0 used to override the recovered validity bit. 0 = use validity bit. 1 = ignore validity bit. table 47 s/pdif rx error mask register
pre-production wm8777 w pp rev 3.0 january 2005 55 the circuit for dealing with unlock, validity, parity and bip errors is shown in figure 26. int serial interface readback mask bit[0/1/2/3] error bit[0/1/2/3] registerreaddone set clr set domiant figure 26 s/pdif error handling circuit for unlock, validity, parity and bip errors non-audio detection non-audio data is indicated by the audio_n and pcm_n bits. audio_n is recovered from the channel status block. pcm_n is set on detection of the 96-bit iec-61937 non-audio data sync code, embedded in the data section of the s/pdif frame. when either the audio_n or pcm_n bits are set in the error register, and dac1 is being used for playback, the dac will be muted automatically using the softmute feature. as described above, any change on audio_n or pcm_n will cause an interrupt to be generated. if the mask register bit for audio_n or pcm_n is set, then that signal will not generate an interrupt but will still mute the dac. if non-audio data is detected and the dac has been muted, the user must ensure that audio data is being input, then clear the error register. the mute on the dac will be removed when the wm8777 detects that audio data is being received. general purpose input and output (gpio) pins the wm8777 has four pins which can be additionally configured as gpios, using the registers shown in table 48. the gpio pins can be used to output control and status data decoded by the s/pdif receiver register address bit label default description 3:0 gpio1op[3:0] 0000 (47h) gpio control 1 7:4 gpio2op[3:0] 0001 3:0 gpio3op[3:0] 0010 (48h) gpio control 2 7:4 gpomodeop [3:0] 1010 0000 = int 0001 = v - validity 0010 = u - user data bit 0011 = c - channel status data 0100 = p - parity bit 0101 = non-audio (audio_n || pcm_n) 0110 = unlock 0111 = csud (channel status registers updated) 1000 = zero flag 1 output 1001 = zero flag 2 output 1010 = gpiox set as s/pdif input (standard cmos input buffer). not valid for gpomode. 1011 = gpiox set as s/pdif input (comparator input for ac coupled consumer s/pdif signals). not valid for gpomode. 1100 = sub frame clock (1 = sub-frame1, 0 = sub- frame2) 1101 = start of block signal table 48 gpio control registers
wm8777 pre-production w pp rev 3.0 january 2004 56 dac control registers dac input control the primary audio interface has a separate input pin for each stereo dac. any input pin can be routed to any dac using the dacxsel register bits. register address bit label default description 1:0 dac1sel [1:0] 00 3:2 dac2sel [1:0] 01 5:4 dac3sel [1:0] 10 (38h) dac digital input selector 7:6 dac4sel [1:0] 11 dac digital input select. 00 = dac takes data from pdataip1 01 = dac takes data from pdataip2 10 = dac takes data from pdataip3 11 = dac takes data from pdataip4 table 49 dac input select register mute modes the wm8777 has individual mutes for each of the four dac channels. setting mute for a channel will apply a soft mute to the input of the digital filters of the channel muted. dmute[0] mutes dac channel 1, dmute[1] mutes dac channel 2, dmute[2] mutes dac channel 3 and dmute[3] mutes dac channel 4. setting the muteall register bit will apply a 'soft' mute to the input of all the dac digital filters register address bit label default description 3:0 dmute[3:0] 0000 dac channel soft mute enables: dmute[0] = 1, enable softmute on dac1. dmute[1] = 1, enable softmute on dac2. dmute[2] = 1, enable softmute on dac3. dmute[3] = 1, enable softmute on dac4. (16h) mute control 4 muteall 0 dac channel master soft mute. mutes all dac channels: 0 = disable softmute on all dacs. 1 = enable softmute on all dacs. table 50 mute registers
pre-production wm8777 w pp rev 3.0 january 2005 57 figure 27 application and release of soft mute figure 27 shows the application and release of mute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when mute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards v mid with a time constant of approximately 64 input samples. if mute is applied to all channels for 1024 or more input samples the dac will be muted if izd is set. when mute is de-asserted, the output will restart immediately from the current input sample. note that all other means of muting the dac channels: setting the pl[3:0] bits to 0, setting the pdwn bit or setting attenuation to 0 will cause much more abrupt muting of the output. the record outputs may be enabled by setting recen, where recen enables the rec1l and rec1r outputs. register address bit label default description 6:5 reclen 00 recl output enable 00 = rec output muted 01 = rec output adcl 10 = rec output dac1l (16h) mute control 8:7 recren 00 recr output enable 00 = rec output muted 01 = rec output adcr 10 = rec output dac1r table 51 rec enable registers -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s)
wm8777 pre-production w pp rev 3.0 january 2004 58 zero flag output the wm8777 has a zero detect circuit for each dac channel which detects when 1024 consecutive zero samples have been input. two zero flag outputs (zflag1 and zflag2) may be output through the gpio pins which may then be used to control external muting circuits. a 1 on zflag1 or zflag2 indicates a zero detect. the zero detect may also be used to automatically enable the dac mute by setting izd. the zero flag output may be disabled by setting dzfm to 0000. the zero flag signal for a dac channel will only be a 1 if that channel is disabled as an input to the output summing stage. register address bit label default description (17h) dac control 7:4 dzfm[3:0] 0000 selects the ouput for zflg1 and zflg2 pins (see table 53). 1 = indicates 1024 consecutive zero input samples on the channels selected 0 = indicates at least one of selected channels has non zero sample in last 1024 inputs table 52 dzfm register dzfm[3:0] zflag1 zflag2 0000 zero flag disabled zero flag disabled 0001 all channels zero all channels zero 0010 left channels zero right channels zero 0011 channel 1 zero channels 2-4 zero 0100 channel 1 zero channel 2 zero 0101 channel 1 zero channel 3 zero 0110 channel 1 zero channel 4 zero 0111 channel 2 zero channel 3 zero 1000 channel 2 zero channel 4 zero 1001 channel 3 zero channel 4 zero 1010 channels 1-3 zero channel 4 zero 1011 channel 1 zero channels 2 and 3 zero 1100 channel 1 left zero channel 1 right zero 1101 channel 2 left zero channel 2 right zero 1110 channel 3 left zero channel 3 right zero 1111 channel 4 left zero channel 4 right zero table 53 zero flag output select infinite zero detect setting the izd register bit will enable the internal infinite zero detect function: register address bit label default description (15h) dac attenuation control 2 izd 0 infinite zero detection circuit control and automute control 0 = infinite zero detect automute disabled 1 = infinite zero detect automute enabled table 54 izd register with izd enabled, applying 1024 consecutive zero input samples each stereo channel will cause that stereo channels outputs to be muted. mute will be removed as soon as any channel receives a non- zero input.
pre-production wm8777 w pp rev 3.0 january 2005 59 de-emphasis mode a digital de-emphasis filter may be applied to each dac channel. the de-emphasis filter for each stereo channel is enabled under the control of deemp[3:0]. deemp[0] enables the de-emphasis filter for channel 1, deemp[1] enables the de-emphasis filter for channel 2, deemp[2] enables the de-emphasis filter for channel 3 and deemp[3] enables the de-emphasis filter for channel 4. register address bit label default description (17h) dac control 3:0 deemp[3:0] 0000 de-emphasis mode select: deemph[0] = 1, enable de- emphasis on dac1. deemph[1] = 1, enable de- emphasis on dac2. deemph[2] = 1, enable de- emphasis on dac3. deemph[3] = 1, enable de- emphasis on dac4. table 55 de-emphasis register refer to figure 39, figure 40, figure 41, figure 42, figure 43 and figure 44 for details of the de- emphasis modes at different sample rates. dac output control the dac output control word determines how the left and right inputs to the audio interface are applied to the left and right dacs: register address bit label default description pl[3:0] left output right output 0000 mute mute 0001 left mute 0010 right mute 0011 (l+r)/2 mute 0100 mute left 0101 left left 0110 right left 0111 (l+r)/2 left 1000 mute right 1001 left right 1010 right right 1011 (l+r)/2 right 1100 mute (l+r)/2 1101 left (l+r)/2 1110 right (l+r)/2 (15h) dac attenuation control 8:5 pl[3:0] 1001 1111 (l+r)/2 (l+r)/2 table 56 dac attenuation register (pl) dac oversampling rate select control bit dacosr allow the user to select the dac internal signal processing oversampling rate. operation is described in table 18 and table 19. register address bit label default description (19h) dac oversampling rate select 3 dacosr 0 dac oversampling rate select 0: 128x oversampling 1: 64x oversampling table 57 dac oversampling rate
wm8777 pre-production w pp rev 3.0 january 2004 60 attenuator control mode setting the atc register bit causes the left channel attenuation settings to be applied to both left and right channel dacs from the next audio input sample. no update to the attenuation registers is required for atc to take effect. when the atc register bit is unset the right channel gain is applied form the new audio input sample. register address bit label default description (15h) dac attenuation control 1 dacatc 0 attenuator control 0 = all dacs use attenuations as programmed. 1 = right channel dacs use corresponding left dac attenuations table 58 dac attenuation register (dacatc) analogue volume control the dac volume may be adjusted independently in both the analogue and digital domain using separate volume control registers. register address bit label default description 6:0 frontla [6:0] 1101011 (0db) analogue attenuation control for frontl in 1db steps. see table 60. 7 frontlzcen 0 frontl zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (00h) analogue attenuation frontl 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store frontl in intermediate latch (no change to output) 1 = store frontl and update attenuation on all channels. 6:0 frontra [6:0] 1101011 (0db) analogue attenuation control for frontr in 1db steps. see table 60. 7 frontrzcen 0 frontr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (01h) analogue attenuation frontr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store frontr in intermediate latch (no change to output) 1 = store frontr and update attenuation on all channels. 6:0 cntra [6:0] 1101011 (0db) analogue attenuation control for cntr in 1db steps. see table 60. 7 cntrzcen 0 cntr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (02h) analogue attenuation cntr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store cntr in intermediate latch (no change to output) 1 = store cntr and update attenuation on all channels. 6:0 lfea [6:0] 1101011 (0db) analogue attenuation control for lfe in 1db steps. see table 60. 7 lfezcen 0 lfe zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (03h) analogue attenuation lfe 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store lfe in intermediate latch (no change to output) 1 = store lfe and update attenuation on all channels.
pre-production wm8777 w pp rev 3.0 january 2005 61 register address bit label default description 6:0 surla [6:0] 1101011 (0db) analogue attenuation control for surl in 1db steps. see table 60. 7 surlzcen 0 surl zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (04h) analogue attenuation surl 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store surl in intermediate latch (no change to output) 1 = store surl and update attenuation on all channels. 6:0 surra [6:0] 1101011 (0db) analogue attenuation control for sur right in 1db steps. 7 surrzcen 0 surr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (05h) analogue attenuation surr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store surr in intermediate latch (no change to output) 1 = store surr and update attenuation on all channels. 6:0 auxla[6:0] 1101011 (0db) analogue attenuation control for auxl in 1db steps. see table 60. 7 auxlzcen 0 auxl zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (06h) analogue attenuation auxl 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store auxl in intermediate latch (no change to output) 1 = store auxl and update attenuation on all channels. 6:0 auxra[6:0] 1101011 (0db) analogue attenuation control for auxr in 1db steps. see table 60. 7 auxrzcen 0 auxr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (07h) analogue attenuation auxr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store auxr in intermediate latch (no change to output) 1 = store auxr and update attenuation on all channels. 6:0 hpla[6:0] 1101011 (0db) analogue attenuation control for hphonel in 1db steps. see table 60. 7 hplzcen 0 hphonel zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (08h) analogue attenuation hphonel 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store hphonel in intermediate latch (no change to output) 1 = store hphonel and update attenuation on all channels. 6:0 hpra[6:0] 1101011 (0db) analogue attenuation control for hphoner in 1db steps. see table 60. 7 hprzcen 0 hphoner zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (09h) analogue attenuation hphoner 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store hphoner in intermediate latch (no change to output) 1 = store hphoner and update attenuation on all channels.
wm8777 pre-production w pp rev 3.0 january 2004 62 register address bit label default description 6:0 masta[6:0] 1101011 (0db) analogue attenuation control for all dac gains in 1db steps. see table 60. 7 mzcen 0 master zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled (0ah) analogue attenuation master (all channels) 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store gains in intermediate latch (no change to output) 1 = store gains and update attenuation on all channels. table 59 analogue attenuation registers each analogue output channel volume can be controlled digitally in an analogue volume stage after the dac. attenuation is 0db by default but can be set between +20db and C100db in 1db steps using the 7 attenuation control words. all attenuation registers are double latched allowing new values to be pre-latched to several channels before being updated synchronously. setting the update bit on any attenuation write will cause all pre-latched values to be immediately applied to the dac channels. a master attenuation register is also included, allowing all volume levels to be set to the same value in a single write. note: the update bit is not latched. if update=0, the attenuation value will be written to the pre- latch but not applied to the relevant ouptut. if update=1, all pre-latched values will be applied from the next input sample. writing to masta[6:0] overwrites any values previously sent to frontl[6:0], cntr[6:0], surl[6:0], auxl[6:0], frontr[6:0], lfe[6:0], s urr[6:0 ], auxr[6:0]. register bits frontl and frontr control the left and right channel attenuation of the front channels. register bits cntr and lfe control the left and right channel attenuation of cntr and lfe respectively. register bits surl and surr control the left and right channel attenuation of surround channels. register bits auxl and auxr control the left and right channel attenuation of the auxiliary channel. register bits masta can be used to control attenuation of all channels. table 60 shows how the attenuation levels are selected from the 7-bit words. l/ra x [6:0] attenuation level 00(hex) - db (mute) : : 06(hex) - db (mute) 07(hex) -100db : : 6b(hex) 0db (default) 7d(hex) +18db 7e(hex) +19db 7f(hex) +20db table 60 analogue volume control attenuation levels in addition a zero cross detect circuit is provided for each analogue output volume under the control of bit 7 (xzcen) in each analogue attenuation register. when zcen is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. this minimises audible cli cks and zipper noise as the gain values change. a timeout clock is also provided which will generate an update after a minimum of 131072 master clo cks ( ~10.5ms with a master clock of 12.288mhz). the timeout clock may be disabled by setting tocdac. register address bit label default description (15h) timeout clock disable 4 tocdac 0 dac analogue zero cross detect timeout disable 0 = timeout enabled 1 = timeout disabled table 61 timeout clock disable register
pre-production wm8777 w pp rev 3.0 january 2005 63 dac digital volume control the dac volume may also be adjusted in the digital domain using independent digital attenuation control registers register address bit label default description 7:0 lda1[7:0] 11111111 (0db) digital attenuation control for dac1 left channel (lsumop) in 0.5db steps. see table 63 (0bh) digital attenuation dacl1 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda1 in intermediate latch (no change to output) 1 = store lda1 and update attenuation on all channels 7:0 rda1[6:0] 11111111 (0db) digital attenuation control for dac1 right channel (rsumop) in 0.5db steps. see table 63 (0ch) digital attenuation dacr1 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda1 in intermediate latch (no change to output) 1 = store rda1 and update attenuation on all channels. 7:0 lda2[7:0] 11111111 (0db) digital attenuation control for dac2 left channel (cntsop) in 0.5db steps. see table 63 (0dh) digital attenuation dacl2 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda2 in intermediate latch (no change to output) 1 = store lda2 and update attenuation on all channels. 7:0 rda2[7:0] 11111111 (0db) digital attenuation control for dac2 right channel (lfesop) in 0.5db steps. see table 63 (0eh) digital attenuation dacr2 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda2 in intermediate latch (no change to output) 1 = store rda2 and update attenuation on all channels. 7:0 lda3[7:0] 11111111 (0db) digital attenuation control for dac3 left channel (lsursop) in 0.5db steps. see table 63 (0fh) digital attenuation dacl3 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda3 in intermediate latch (no change to output) 1 = store lda3 and update attenuation on all channels. 7:0 rda3[7:0] 11111111 (0db) digital attenuation control for dac3 right channel (rsursop) in 0.5db steps. see table 63 (10h) digital attenuation dacr3 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda3 in intermediate latch (no change to output) 1 = store rda3 and update attenuation on all channels. 7:0 lda4[7:0] 11111111 (0db) digital attenuation control for dac4 left channel (lauxsop) in 0.5db steps. see table 63 (11h) digital attenuation dacl4 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda4 in intermediate latch (no change to output) 1 = store lda4 and update attenuation on all channels. 7:0 rda4[7:0] 11111111 (0db) digital attenuation control for dac4 right channel (rauxsop) in 0.5db steps. see table 63 (12h) digital attenuation dacr4 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda4 in intermediate latch (no change to output) 1 = store rda4 and update attenuation on all channels. 7:0 mastda[7:0] 11111111 (0db) digital attenuation control for all dac channels in 0.5db steps. see table 63 (13h) digital attenuation master (all channels) 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain in intermediate latch (no change to output) 1 = store gain and update attenuation on all channels. table 62 digital attenuation registers
wm8777 pre-production w pp rev 3.0 january 2004 64 l/rdax[7:0] attenuation level 00(hex) - db (mute) 01(hex) -127.5db : : : : : : fe(hex) -0.5db ff(hex) 0db table 63 digital volume control attenuation levels the digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. this is enabled by control bit dzcen. register address bit label default description (15h) dac attenuation control 0 dzcen 0 dac digital volume zero cross enable: 0 = zero cross detect disabled 1 = zero cross detect enabled table 64 digital zero cross register dac output phase the dac phase control word determines whether the output of each dac is non-inverted or inverted register address bit label default description (14h) dac output phase 7:0 phase [7:0] 00000000 controls phase of dac outputs phase[0] = 1 inverts phase of dac1l output phase[1] = 1 inverts phase of dac1r output phase[2] = 1 inverts phase of dac2l output phase[3] = 1 inverts phase of dac2r output phase[4] = 1 inverts phase of dac3l output phase[5] = 1 inverts phase of dac3r output phase[6] = 1 inverts phase of dac4l output phase[7] = 1 inverts phase of dac4r output table 65 dac output phase register
pre-production wm8777 w pp rev 3.0 january 2005 65 output select and enable control register bits mx1[2:0] to mx4[2:0] control the output select. the output select block consists of a summing stage and an input select switch for each input allowing each signal to be output individually or summed with other signals and output on each analogue output. the default for all outputs is dac playback only. vout1/2/3 may be selected to output dac playback, aux, analogue bypass or a sum of these using the output select controls mx1/2/3[2:0]. vout4 may be selected to output dac playback, analogue bypass or a sum of these signals using mx4[1:0]. it is recommended that bypass is not selected for output on more than two stereo channels simultaneously to avoid overloading the input buffer, resulting in a decrease in performance. the output mixers and pgas can be powered down under control of outpd1/2/3/4. each stereo channel may be powered down separately. setting outpd1/2/3/4 will power off the mixer and pga and switch the analogue outputs voutl/r to vmiddac to maintain a dc level on the output. register address bit label default description 2:0 mx1[2:0] 001 (dac playback) vout1 output select (see figure 28) (32h) output mux and powerdown control 1 5:3 mx2[2:0] 001 (dac playback) vout2 output select (see figure 28) 2:0 mx3[2:0] 001 (dac playback) vout3 output select (see figure 28) (33h) output mux and powerdown control 2 4:3 mx4[1:0] 01 (dac playback) vout4 output select (see figure 29) table 66 output mux register figure 28 mx1/2/3[2:0] output select figure 29 mx4[1:0] output select
wm8777 pre-production w pp rev 3.0 january 2004 66 adc control registers adc gain control the adc has an analogue input pga and digital gain control for each stereo channel. both the analogue and digital gains are adjusted by the same register, lag for the left and rag for the right. the analogue pga has a range of +24db to -21db in 0.5db steps. the digital gain control allows further attenuation (after the adc) from -21.5db to -103db in 0.5db steps. table 68 shows how the register maps the analogue and digital gains. register address bit label default description 7:0 lag[7:0] 11001111 (0db) attenuation control for left channel adc gain in 0.5db steps. see table 68 (2eh) attenuation adc left 8 zclen 0 zero cross enable for left channel adc 0 = disable zero cross 1 = enable zero cross 7:0 rag[7:0] 11001111 (0db) attenuation control for right channel adc gain in 0.5db steps. see table 68 (2fh) attenuation adc right 8 zcren 0 zero cross enable for right channel adc 0 = disable zero cross 1 = enable zero cross 0 mutel 0 left channel mute control 0 = channel not muted 1 = channel muted 1 muter 0 left channel mute control 0 = channel not muted 1 = channel muted 2 adcatc 0 attenuator control 0 = adc use attenuations as programmed. 1 = right channel adc use corresponding left adc attenuations (30h) attenuation control 3 toadc 0 time out clock enable/disable 0 = time out clock enabled. 1 = time out clock disabled. table 67 adc attenuation and mute registers lag/rag[7:0] attenuation level (at output) analogue pga digital attenuation 00(hex) - db (mute) -21db digital mute 01(hex) -103db -21db -82db : : : : a4(hex) -21.5db -21db -0.5db a5(hex) -21db -21db 0db : : : : cf(hex) 0db 0db 0db : : : : fe(hex) +23.5db +23.5db 0db ff(hex) +24db +24db 0db table 68 analogue and digital gain mapping for adc in addition a zero cross detect circuit is provided for the output pga volume under the control of bit 7 (zcen) in the each attenuation register. when zcen is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. this minimises audible clicks and zipper noise as the gain values change. a timeout clock is also provided which will generate an update after a minimum of 131072 master clo cks (= ~10.5ms with a master clock of 12.288mhz). the timeout clock may be disabled by setting toadc.
pre-production wm8777 w pp rev 3.0 january 2005 67 each adc channel also has an individual mute control bit, which mutes the input to the adc. the adcatc control bit allows the user to write the same attenuation value (lag) to both left and right volume control registers, saving on software writes. when setting the adcatc function it is up to the user to write a new gain value to take effect on both channels. when unsetting the adcatc function it is up to the user to write a new gain to both the left and right channel gains. the atc function has no effect when the alc is enabled. the adc volume and mute also applies to the bypass signal path. adc oversampling rate select the signal processing for the wm8777 typically operates at an oversampling rate of 128fs for the adc (adcosr=0). the exception to this is for operation with a 128/192fs system clock, where the oversampling rate is 64fs (adcosr=1). for the adc operation at 96khz in 256fs or 384fs mode it is recommended that the user set the adcosr bit. this changes the adc signal processing oversample rate from 128fs to 64fs. for the adc operation at 192khz in 128fs or 192fs mode it is recommended that the user set the adcosr bit. this changes the adc signal processing oversample rate from 64fs to 32fs. the adc digital filters contain a digital highpass filter. this defaults to enabled and can be disabled using software control bit adchpd. if the dac and adc are using the same mclk source, and they are in compatible fs modes the adc and dac will try to lock their respective clock generators together. this reduces the digital noise on chip and helps the performance of the device. by default this is enabled, but can be disabled by setting sync to 1. register address bit label default description 6 adchpd 0 adc highpass filter disable: 0 = highpass filter enabled 1 = highpass filter disabled 7 adcosr 0 adc oversample rate select 0 = 128x oversampling 1 = 64x oversampling (1bh) adc interface control 8 sync 0 sync adc and dac together. 0 = enable sync function 1 = disable sync function table 69 adc functions register adc input mux register address bit label default description (31h) adc mux and powerdown control 5:0 ain[5:0] 00000 adc input mixer control bits (see table 71) table 70 adc input mux register register bits ain[5:0] control the left and right channel inputs into the stereo adc. the default is ain1. however if the analogue input buffer is powered down, by setting ainpd, then all 12-channel mux inputs are switched to buffered vmidadc. ain[5:0] adc input 00000 mute 00001 ain1 00010 ain2 00011 ain1 + ain2 00100 ain3 00101 ain3 + ain1 . 11111 ain6 + ain5 + ain4 +ain3 + ain2 + ain1 table 71 adc input mux control
wm8777 pre-production w pp rev 3.0 january 2004 68 limiter / automatic level control (alc) the wm8777 has an automatic pga gain control circuit, which can function as a peak limiter or as an automatic level control (alc). in peak limiter mode, a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the adc. when the signal returns to a level below the threshold, the pga gain is slowly returned to its starting level. the peak limiter cannot increase the pga gain above its static level. figure 30 limiter operation in alc mode, the circuit aims to keep a constant recording volume irrespective of the input signal level. this is achieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary. figure 31 alc operation hold time decay time attack time input signal signal after alc pga gain alc target level input signal signal after pga pga gain limiter threshold attack time decay time
pre-production wm8777 w pp rev 3.0 january 2005 69 the gain control circuit is enabled by setting the lcen control bit. the user can select between limiter mode and three different alc modes using the lcsel control bits. register address bit label default description (1eh) alc control 2 8 lcen 0 enable the pga gain control circuit. 0 = pga gain control disabled 1 = pga gain control enabled (1dh) alc control 1 8:7 lcsel[1:0] 00 alc/limiter function select 00 = limiter 01 = alc right channel only 10 = alc left channel only 11 = alc stereo table 72 alc control registers the limiter function only operates in stereo, which means that the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right pgas, so that the stereo image is preserved. however, the alc function can also be enabled on one channel only. in this case, only one pga is controlled by the alc mechanism, while the other channel runs independently with its pga gain set through the control register. when enabled, the threshold for the limiter or target level for the alc is programmed using the lct control bits. this allows the threshold/target level to be programmed between -1db and -16db in 1db steps. note that for the alc, target levels of -1db and -2db give a threshold of -3db. this is because the alc can give erroneous operation if the target level is set too high. register address bit label default description (1dh) alc control 1 3:0 lct[3:0] 1011 (-6db) limiter threshold/alc target level in 1db steps. 0000 = -16db fs 0001 = -15db fs 1101 = -3db fs 1110 = -2db fs 1111 = -1db fs table 73 limiter threshold register attack and decay times the limiter and alc have different attack and decay times which determine their operation. however, the attack and decay times are defined slightly differently for the limiter and for the alc. dcy and atk control the decay and attack times, respectively. decay time (gain ramp-up). when in alc mode, this is defined as the time that it takes for the pga gain to ramp up across 90% of its range (e.g. from C21db up to +20 db). when in limiter mode, it is defined as the time it takes for the gain to ramp up by 6db. the decay time can be programmed in power-of-two (2 n ) steps. for the alc this gives times from 33.6ms, 67.2ms, 134.4ms etc. to 34.41s. for the limiter this gives times from 1.2ms, 2.4ms etc., up to 1.2288s. however, the decay time for the limiter can also be made dependant on the input frequency by setting the fdecay control bit. for a 1khz input signal this gives decay times of 24ms, 48ms etc., up to 24.576s. attack time (gain ramp-down) when in alc mode, this is defined as the time that it takes for the pga gain to ramp down across 90% of its range (e.g. from +20db down to -21db gain). when in limiter mode, it is defined as the time it takes for the gain to ramp down by 6db. the attack time can be programmed in power-of-two (2 n ) steps, from 8.4ms, 16.8ms, 33.6ms etc. to 8.6s for the alc and from 250us, 500us, etc. up to 256ms. the time it takes for the recording level to return to its target value or static gain value therefore depends on both the attack/decay time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the attack/decay time.
wm8777 pre-production w pp rev 3.0 january 2004 70 register address bit label default description lc attack (gain ramp-down) time 3:0 atk[3:0] 0010 alc mode 0000 = 8.4ms 0001 = 16.8ms 0010 = 33.6ms (time doubles with every step) 1010 or higher = 8.6s limiter mode 0000 = 250us 0001 = 500us 0010 = 1ms (time doubles with every step) 1010 or higher = 256ms lc decay (gain ramp-up) time 7:4 dcy[3:0] 0011 alc mode 0000 = 33.5ms 0001 = 67.2ms 0010 = 134.4ms .(time doubles for every step) 1010 or higher = 34.41ms limiter mode 0000 = 1.2ms 0001 = 2.4ms 0010 = 4.8ms .(time doubles for every step) 1010 or higher = 1.2288s frequency dependant decay (limiter only) 0 = frequency dependent delay disabled 1 = frequency dependent delay enabled dcy 20khz input (or disabled) 1khz input (1fh) alc control 3 8 fdecay 0 0000 0001 0010 1010 or higher 1.2ms 2.4ms 4.8ms 1.2288ms 24ms 28ms 96ms 24.576s table 74 alc attack and decay registers transient window (limiter only) to prevent the limiter responding to short duration high amplitude signals (such as hand-claps in a live performance), the limiter has a programmable transient window preventing it responding to signals above the threshold until their duration exceeds the window period. the transient window is set in register tranwin. register address bit label default description (21h) limiter control 6:4 tranwin [2:0] 010 length of transient window 000 = 0us (disabled) 001 = 62.5us 010 = 125us .. 111 = 4ms table 75 transient window register zero cross the pga has a zero cross detector to prevent gain changes introducing noise to the signal. in alc mode the register bit alczc allows this to be turned on if desired. register address bit label default description (1eh) alc control 2 7 alczc 0 (disabled) alc zero cross detection circuit. 0 = zero cross detection disabled. 1 = zero cross detection enabled. table 76 alc zero cross register when the limiter is enabled the zero cross detector on the pga is automatically enabled to ensure that no noise is introduced during gain changes.
pre-production wm8777 w pp rev 3.0 january 2005 71 maximum gain (alc only) and maximum attenuation to prevent low level signals being amplified too much by the alc, the maxgain register sets the upper limit for the gain. this prevents low level noise being over-amplified. the maxgain register has no effect on the limiter operation. the maxatten register has different operation for the limiter and for the alc. for the limiter it defines the maximum attenuation below the static (user programmed) gain. for the alc, it defines the lower limit for the gain. register address bit label default description (1dh) alc control 1 6:4 maxgain[2:0] 111 (+24db) set maximum gain for the pga (alc only) 111 = +24db 110 = +20db ..(-4db steps) 010 = +4db 001 = 0db 000 = 0db maximum attenuation of pga (21h) limiter control 3:0 maxatten [3:0] 0110 limiter (attenuation below static) 0000 = -3db 0001 = -4db 0010 = -5db . (-1db steps) 1001 = -12db alc (lower pga gain limit) 1010 or lower = -1db 1011 = -5db .. (-4db steps) 1110 = -17db 1111 = -21db table 77 alc maxgain and maxatten registers hold time (alc only) the alc also has a hold time, which is the time delay between the peak level detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7ms. alternatively, the hold time can also be set to zero. the hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. register address bit label default description (1eh) alc control 2 3:0 hld[3:0] 0000 alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms (time doubles with every step) 1111 = 43.691s table 78 alc hold time register overload detector (alc only) to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes an overload detector. if the adc input signal exceeds 87.5% of full scale (C1.16db), the pga gain is ramped down at the maximum attack rate (as when atk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. ( note : if atk = 0000, then the overload detector makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used).
wm8777 pre-production w pp rev 3.0 january 2004 72 noise gate (alc only) when the signal is very quiet and consists mainly of noise, the alc function may cause noise pumping, i.e. loud hissing noise during silence periods. the wm8777 has a noise gate function that prevents noise pumping by comparing the signal level at the ainl1/2/3/4/5 and/or ainr1/2/3/4/5 pins against a noise gate threshold, ngth. the noise gate cuts in when: ? signal level at adc [db] < ngth [db] + pga gain [db] + mic boost gain [db] this is equivalent to: ? signal level at input pin [db] < ngth [db] when the noise gate is triggered, the pga gain is held constant (preventing it from ramping up as it would normally when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 6db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with setCup of the function. note that the noise gate only works in conjunction with the alc function, and always operates on the same channel(s) as the alc (left, right, both, or none). register address bit label default description 0 ngat 0 noise gate function enable 0 = noise gate disabled 1 = noise gate enabled (20h) noise gate control 4:2 ngth[2:0] 000 noise gate threshold (with respect to adc output level) 000 = -78dbfs 001 = -72dbfs 6 db steps 110 = -42dbfs 111 = -30dbfs table 79 noise gate registers note: the noise gate should be set after the alc to ensure correct operation. software register reset writing to register 1111111 will cause a register reset, resetting all register bits to their default values. note that the wm8777 is powered down by default so writing to this register will power down the device. table 80 software reset register register address bit label default description (7fh) software reset 8:0 reset writing to this register will apply a reset to the device registers.
pre-production wm8777 w pp rev 3.0 january 2005 73 register map the complete register map is shown below. the detailed description can be found in the relevant text of the device description. the wm8777 can be configured using the control interface. all unused bits should be set to 0. register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default r0(00h) 0 0 0 0 0 0 0 update frontlzcen frontla[6:0] x01101011 r1(01h) 0 0 0 0 0 0 1 update frontrzcen frontra[6:0] x01101011 r2(02h) 0 0 0 0 0 1 0 update cntrzcen cntra[6:0] x01101011 r3(03h) 0 0 0 0 0 1 1 update lfezcen lfea[6:0] x01101011 r4(04h) 0 0 0 0 1 0 0 update surlzcen surla[6:0] x01101011 r5(05h) 0 0 0 0 1 0 1 update surlzcen surra[6:0] x01101011 r6(06h) 0 0 0 0 1 1 0 update auxlzcen auxla[6:0] x01101011 r7(07h) 0 0 0 0 1 1 1 update auxrzcen auxra[6:0] x01101011 r8(08h) 0 0 0 1 0 0 0 update hplzcen hpla[6:0] x01101011 r9(09h) 0 0 0 1 0 0 1 update hprzcen hpra[6:0] x01101011 r10(0ah) 0 0 0 1 0 1 0 update mzcen masta[6:0] x01101011 r11(0bh) 0 0 0 1 0 1 1 update lda1[7:0] x11111111 r12(0ch) 0 0 0 1 1 0 0 update rda1[7:0] x11111111 r13(0dh) 0 0 0 1 1 0 1 update lda2[7:0] x11111111 r14(0eh) 0 0 0 1 1 1 0 update rda2[7:0] x11111111 r15(0fh) 0 0 0 1 1 1 1 update lda3[7:0] x11111111 r16(10h) 0 0 1 0 0 0 0 update rda3[7:0] x11111111 r17(11h) 0 0 1 0 0 0 1 update lda4[7:0] x11111111 r18(12h) 0 0 1 0 0 1 0 update rda4[7:0] x11111111 r19(13h) 0 0 1 0 0 1 1 update mastda[7:0] x11111111 r20(14h) 0 0 1 0 1 0 0 0 phase[7:0] 000000000 r21(15h) 0 0 1 0 1 0 1 pl[3:0] tocdac 0 izd dacatc dzcen 100100000 r22(16h) 0 0 1 0 1 1 0 recren[1:0] reclen[1:0] muteall dmute[3:0] 000000000 r23(17h) 0 0 1 0 1 1 1 0 dzfm[3:0] deemp[3:0] 000000000 r24(18h) 0 0 1 1 0 0 0 0 mlckout sr c mclkopen paifrx_wl[1:0] paifrx b c p paifrx lrp paifrx_fmt[1:0] 000100010 r25(19h) 0 0 1 1 0 0 1 paifrx ms paiftx_ms paifrx_rate[2:0] dacosr paiftx_rate[2:0] 000100010 r26(1ah) 0 0 1 1 0 1 0 oscpd spdifrxd spdiftxd dacpd[3:0] adcpd pwdn 111111110 r27(1bh) 0 0 1 1 0 1 1 sync adcosr adchpd paiftx_wl [ 1: 0] paiftx b c p paiftx lrp paiftx_fmt[1:0] 000100010 r28(1ch) 0 0 1 1 1 0 0 reserved 000000000 r29(1dh) 0 0 1 1 1 0 1 lcsel[1:0] maxgain[2:0] lct[3:0] 001111011 r30(1eh) 0 0 1 1 1 1 0 lcen alczc 0 0 0 hld[3:0] 000000000 r31(1fh) 0 0 1 1 1 1 1 fdecay dcy[3:0] atk[3:0] 100110010 r32(20h) 0 1 0 0 0 0 0 0 0 0 0 ngth[2:0] 0 ngat 000000000 r33(21h) 0 1 0 0 0 0 1 0 0 tranwin[2:0] maxatten[3:0] 010100110 r34(22h) 0 1 0 0 0 1 0 0 0 ain6 fbyp fbm fbass[1:0] ftrbl[1:0] 000000000 r35(23h) 0 1 0 0 0 1 1 0 cntr cntrgaiin[2:0] flfe flfegain[2:0] 000000000
wm8777 pre-production w pp rev 3.0 january 2004 74 register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default r36(24h) 0 1 0 0 1 0 0 0 0 0 0 0 rear reargain[2:0] 000000000 r37(25h) 0 1 0 0 1 0 1 0 0 hpsel cbyp cbm cbass[1:0] ctrbl[1:0] 000000000 r38(26h) 0 1 0 0 1 1 0 0 0 0 0 0 clfe clfegain[2:0] 000000000 r39(27h) 0 1 0 0 1 1 1 0 0 0 0 0 surrbyp surl byp auxrbyp auxlbyp 000000000 r40(28h) 0 1 0 1 0 0 0 update 0 0 0 0 fbass[3:0] 000000000 r41(29h) 0 1 0 1 0 0 1 update 0 0 0 0 ftreb[3:0] 000000000 r42(2ah) 0 1 0 1 0 1 0 update 0 0 0 0 cbass[3:0] 000000000 r43(2bh) 0 1 0 1 0 1 1 update 0 0 0 0 ctreb[3:0] 000000000 r44(2ch) 0 1 0 1 1 0 0 updatel updater updatec ftlp[1:0] ftrp[1:0] cntp[1:0] 000000000 r45(2dh) 0 1 0 1 1 0 1 hppd ftrpd ftlpd ctrpd lfepd surrpd surlpd auxrpd auxlpd 111111111 r46(2eh) 0 1 0 1 1 1 0 zclen lag[7:0] 011001111 r47(2fh) 0 1 0 1 1 1 1 zcren rag[7:0] 011001111 r48(30h) 0 1 1 0 0 0 0 0 0 0 0 0 toadc adc at c muter mutel 000000000 r49(31h) 0 1 1 0 0 0 1 ainpd 0 0 ain[5:0] 100000000 r50(32h) 0 1 1 0 0 1 0 outpd2 outpd1 0 mx2[2:0] mx1[2:0] 110001001 r51(33h) 0 1 1 0 0 1 1 outpd4 outpd3 0 0 mx4[1:0] mx3[2:0] 110001001 r52(34h) 0 1 1 0 1 0 0 pll_k[8:0] 100100001 r53(35h) 0 1 1 0 1 0 1 pll_k[17:9] 101111110 r54(36h) 0 1 1 0 1 1 0 pll2tx pll2 ad c pll2 da c 0 clkouts rc pll_k[21:18] 100001101 r55(37h) 0 1 1 0 1 1 1 pll_n[4:0] prescale frac_e n postsca le pllpd 000000011 r56(38h) 0 1 1 1 0 0 0 0 dac4sel[1:0] dac3sel[1:0] dac2sel[1:0] dac1sel[1:0] 011100100 r57(39h) 0 1 1 1 0 0 1 0 chstmode[2:0] preemph[2:0] cpy_n audio_n con/pro 000000000 r58(3ah) 0 1 1 1 0 1 0 0 catcode[7:0] 000000000 r59(3bh) 0 1 1 1 0 1 1 0 chnum2[1:0] chnum1[1:0] srcnum[3:0] 000000000 r60(3ch) 0 1 1 1 1 0 0 0 0 0 clkacu[1:0] freq[3:0] 000110001 r61(3dh) 0 1 1 1 1 0 1 0 orgsamp[3:0] txpaifrx_wl[1:0] maxpaifr xwl 000001011 r62(3eh) 0 1 1 1 1 1 0 0 0 saif_wl [ 1: 0] saif_b c p saif_l rp saif_fmt [ 1: 0] 000100010 r63(3fh) 0 1 1 1 1 1 1 0 0 0 saifclksrc[1:0] sms saifrate[2:0] 000000010 r64(40h) 1 0 0 0 0 0 0 adccl ksrc alwaysva lid fillmode rxinsel[1:0] 0 0 0 spdinmode 000000000 r65(41h) 1 0 0 0 0 0 1 0 saifsrc[1:0] paifsrc[1:0] txrxt hru txsrc[1:0] rx2dac 000010000 r66(42h) 1 0 0 0 0 1 0 0 0 0 fpll[2:0] 0 0 0 000111000 r67(43h) 1 0 0 0 0 1 1 reserved 00000000 r68(44h) 1 0 0 0 1 0 0 reserved 000000000 r69(45h) 1 0 0 0 1 0 1 reserved 000000000 r70(46h) 1 0 0 0 1 1 0 reserved 000000000 r71(47h) 1 0 0 0 1 1 1 0 gpio2op[3:0] gpio1op[3:0] 000010000 r72(48h) 1 0 0 1 0 0 0 0 gpomodeop[3:0] gpio3op[3:0] 010100010 r73(49h) 1 0 0 1 0 0 1 0 mask[7:0] 000000000
pre-production wm8777 w pp rev 3.0 january 2005 75 register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default r74(4ah) 1 0 0 1 0 1 0 0 0 0 readen2 readen 3 0 0 0 0 000000000 r75(4bh) 1 0 0 1 0 1 1 0 spdif_mo de cpy_n pcm_n audio_n bip parityerr validity unlock r76(4ch) 1 0 0 1 1 0 0 read only 1 r77(4dh) 1 0 0 1 1 0 1 read only 2 r78(4eh) 1 0 0 1 1 1 0 read only 3 r79(4fh) 1 0 0 1 1 1 1 read only 4 r80(50h) 1 0 1 0 0 0 0 read only 5 r81(51h) 1 0 1 0 0 0 1 read only 6 r127(7fh ) 1 1 1 1 1 1 1 reset see notes address data default table 81 register map note: any write to r127 causes a software reset.
wm8777 pre-production w pp rev 3.0 january 2004 76 register address bit label default description 6:0 frontla[6:0] 1101011 (0db) analogue attenuation control for frontl in 1db steps. see table 60. 7 frontlzcen 0 frontl zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000000 (00h) analogue attenuation frontl 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store frontl in intermediate latch (no change to output) 1 = store frontl and update attenuation on all channels. 6:0 frontra[6:0] 1101011 (0db) analogue attenuation control for frontr in 1db steps. see table 60. 7 frontrzcen 0 frontr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000001 (01h) analogue attenuation frontr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store frontr in intermediate latch (no change to output) 1 = store frontr and update attenuation on all channels. 6:0 cntra[6:0] 1101011 (0db) analogue attenuation control for cntr in 1db steps. see table 60. 7 cntrzcen 0 cntr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000010 (02h) analogue attenuation cntr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store cntr in intermediate latch (no change to output) 1 = store cntr and update attenuation on all channels. 6:0 lfea[6:0] 1101011 (0db) analogue attenuation control for lfe in 1db steps. see table 60. 7 lfezcen 0 lfe zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000011 (03h) analogue attenuation lfe 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store lfe in intermediate latch (no change to output) 1 = store lfe and update attenuation on all channels. 6:0 surla[6:0] 1101011 (0db) analogue attenuation control for surl in 1db steps. see table 60. 7 surlzcen 0 surl zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000100 (04h) analogue attenuation surl 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store surl in intermediate latch (no change to output) 1 = store surl and update attenuation on all channels. 6:0 surra[6:0] 1101011 (0db) analogue attenuation control for sur right in 1db steps. table 60. 7 surrzcen 0 surr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000101 (05h) analogue attenuation surr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store surr in intermediate latch (no change to output) 1 = store surr and update attenuation on all channels.
pre-production wm8777 w pp rev 3.0 january 2005 77 register address bit label default description 6:0 auxla[6:0] 1101011 (0db) analogue attenuation control for auxl in 1db steps. see table 60. 7 auxlzcen 0 auxl zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000110 (06h) analogue attenuation auxl 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store auxl in intermediate latch (no change to output) 1 = store auxl and update attenuation on all channels. 6:0 auxra[6:0] 1101011 (0db) analogue attenuation control for auxr in 1db steps. see table 60. 7 auxrzcen 0 auxr zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0000111 (07h) analogue attenuation auxr 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store auxr in intermediate latch (no change to output) 1 = store auxr and update attenuation on all channels. 6:0 hpla[6:0] 1101011 (0db) analogue attenuation control for hphonel in 1db steps. see table 60. 7 hplzcen 0 hphonel zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0001000 (08h) analogue attenuation hphonel 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store hphonel in intermediate latch (no change to output) 1 = store hphonel and update attenuation on all channels. 6:0 hpra[6:0] 1101011 (0db) analogue attenuation control for hphoner in 1db steps. see table 60. 7 hprzcen 0 hphoner zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0001001 (09h) analogue attenuation hphoner 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store hphoner in intermediate latch (no change to output) 1 = store hphoner and update attenuation on all channels. 6:0 masta[6:0] 1101011 (0db) analogue attenuation control for all dac gains in 1db steps. see table 60. 7 mzcen 0 master zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled 0001010 (0ah) analogue attenuation master (all channels) 8 update not latched controls simultaneous update of all analogue attenuation latches 0 = store gains in intermediate latch (no change to output) 1 = store gains and update attenuation on all channels. 7:0 lda1[7:0] 11111111 (0db) digital attenuation control for dac1 left channel (lsumop) in 0.5db steps. see table 63 0001011 (0bh) digital attenuation dacl1 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda1 in intermediate latch (no change to output) 1 = store lda1 and update attenuation on all channels 7:0 rda1[6:0] 11111111 (0db) digital attenuation control for dac1 right channel (rsumop) in 0.5db steps. see table 63 0001100 (0ch) digital attenuation dacr1 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda1 in intermediate latch (no change to output) 1 = store rda1 and update attenuation on all channels. 7:0 lda2[7:0] 11111111 (0db) digital attenuation control for dac2 left channel (cntsop) in 0.5db steps. see table 63 0001101 (0dh) digital attenuation dacl2 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda2 in intermediate latch (no change to output) 1 = store lda2 and update attenuation on all channels.
wm8777 pre-production w pp rev 3.0 january 2004 78 register address bit label default description 7:0 rda2[7:0] 11111111 (0db) digital attenuation control for dac2 right channel (lfesop) in 0.5db steps. see table 63 0001110 (0eh) digital attenuation dacr2 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda2 in intermediate latch (no change to output) 1 = store rda2 and update attenuation on all channels. 7:0 lda3[7:0] 11111111 (0db) digital attenuation control for dac3 left channel (lsursop) in 0.5db steps. see table 63 0001111 (0fh) digital attenuation dacl3 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda3 in intermediate latch (no change to output) 1 = store lda3 and update attenuation on all channels. 7:0 rda3[7:0] 11111111 (0db) digital attenuation control for dac3 right channel (rsursop) in 0.5db steps. see table 63 0010000 (10h) digital attenuation dacr3 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda3 in intermediate latch (no change to output) 1 = store rda3 and update attenuation on all channels. 7:0 lda4[7:0] 11111111 (0db) digital attenuation control for dac4 left channel (lauxsop) in 0.5db steps. see table 63 0010001 (11h) digital attenuation dacl4 8 update not latched controls simultaneous update of all attenuation latches 0 = store lda4 in intermediate latch (no change to output) 1 = store lda4 and update attenuation on all channels. 7:0 rda4[7:0] 11111111 (0db) digital attenuation control for dac4 right channel (rauxsop) in 0.5db steps. see table 63 0010010 (12h) digital attenuation dacr4 8 update not latched controls simultaneous update of all attenuation latches 0 = store rda4 in intermediate latch (no change to output) 1 = store rda4 and update attenuation on all channels. 7:0 mastda[7:0] 11111111 (0db) digital attenuation control for all dac channels in 0.5db steps. see table 63 0010011 (13h) digital attenuation master (all channels) 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain in intermediate latch (no change to output) 1 = store gain and update attenuation on all channels. 0010100 (14h) dac output phase 7:0 phase[7:0] 00000000 controls phase of dac outputs phase[0] = 1 inverts phase of dac1l output phase[1] = 1 inverts phase of dac1r output phase[2] = 1 inverts phase of dac2l output phase[3] = 1 inverts phase of dac2r output phase[4] = 1 inverts phase of dac3l output phase[5] = 1 inverts phase of dac3r output phase[6] = 1 inverts phase of dac4l output phase[7] = 1 inverts phase of dac4r output 0 dzcen 0 dac digital volume zero cross enable: 0 = zero cross detect disabled 1 = zero cross detect enabled 1 dacatc 0 attenuator control 0 = all dacs use attenuations as programmed. 1 = right channel dacs use corresponding left dac attenuations 2 izd 0 infinite zero detection circuit control and automute control 0 = infinite zero detect automute disabled 1 = infinite zero detect automute enabled 0010101 (15h) dac attenuation control 4 tocdac 0 dac analogue zero cross detect timeout disable 0 = timeout enabled 1 = timeout disabled
pre-production wm8777 w pp rev 3.0 january 2005 79 register address bit label default description dac output control pl[3:0] left output right output pl[3:0] left output right output 0000 mute mute 1000 mute right 0001 left mute 1001 left right 0010 right mute 1010 right right 0011 (l+r)/2 mute 1011 (l+r)/2 right 0100 mute left 1100 mute (l+r)/2 0101 left left 1101 left (l+r)/2 0110 right left 1110 right (l+r)/2 8:5 pl[3:0] 1001 0111 (l+r)/2 left 1111 (l+r)/2 (l+r)/2 3:0 dmute[3:0] 0000 dac channel soft mute enables: dmute[0] = 1, enable softmute on dac1. dmute[1] = 1, enable softmute on dac2. dmute[2] = 1, enable softmute on dac3. dmute[3] = 1, enable softmute on dac4. 4 muteall 0 dac channel master soft mute. mutes all dac channels: 0 = disable softmute on all dacs. 1 = enable softmute on all dacs. 6:5 reclen 00 recl output enable 00 = rec output muted 01 = rec output adcl 10 = rec output dac1l 0010110 (16h) mute control 8:7 recren 00 recr output enable 00 = rec output muted 01 = rec output adcr 10 = rec output dac1r 3:0 deemp[3:0] 0000 de-emphasis mode select: deemph[0] = 1, enable de-emphasis on dac1. deemph[1] = 1, enable de-emphasis on dac2. deemph[2] = 1, enable de-emphasis on dac3. deemph[3] = 1, enable de-emphasis on dac4. 0010111 (17h) dac control 7:4 dzfm[3:0] 0000 selects the ouput for zflg1 and zflg2 pins (see table 53). 1 = indicates 1024 consecutive zero input samples on the channels selected 0 = indicates at least one of selected channels has non zero sample in last 1024 inputs 1:0 paifrx_fmt [1:0] 10 interface format select 00 = right justified mode 01 = left justified mode 10 = i 2 s mode 11 = dsp (early or late) mode pdataiplrc polarity or dsp early/late mode select 2 paifrx_lrp 0 left justified / right justified / i 2 s 0 =standard pdataiplrc polarity 1 =inverted pdataiplrc polarity dsp mode 0 = early dsp mode 1 = late dsp mode 0011000 (18h) primary interface control (rx) 3 paifrx_bcp 0 pbclk polarity 0 = normal - din[3:0], pdataiplrc and pdataoplrc sampled on rising edge of pbclk; pdataop changes on falling edge of pbclk. 1 = inverted - din[3:0], pdataiplrc and pdataoplrc sampled on falling edge of pbclk; pdataop changes on rising edge of pbclk.
wm8777 pre-production w pp rev 3.0 january 2004 80 register address bit label default description 5:4 paifrx_wl [1:0] 10 input word length 00 = 16-bit mode 01 = 20-bit mode 10 = 24-bit mode 11 = 32-bit mode (not supported in right justified mode) 6 mclkopen 0 mclk pin output enable 0 = mclk pin is an input 1 = mclk pin is an output (see mclkoutsrc below) 7 mclkoutsrc 0 mclk pin output source 0 = pll 1 = crystal clock output. 2:0 paiftx_rate [2:0] 010 master mode mclk:pdataoplrc ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs 3 dacosr 0 dac oversample rate select: 0 = 128x oversampling 1 = 64x oversampling 6:4 paifrx_rate [2:0] 010 master mode mclk:pdataiplrc ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs 7 paiftx_ms 0 master/slave interface mode select. if a dcclksrc is set high then this register control whether the adc clocks are in master or slave mode/ 0 = slave mode C pdataoplrc and adcpbclk are inputs 1 = master mode C pdataoplrc and adcpbclk are outputs 0011001 (19h) master mode control 8 paifrx_ms 0 maser/slave interface mode select 0 = slave mode C pdataoplrc, pdataiplrc and pbclk are inputs 1 = master mode C pdataoplrc, pdataiplrc and pbclk are outputs note if adcclksrc is set high then this register only controls pdataiplrc and pbclk. 0 pwdn 0 chip powerdown control (works in tandem with the other powerdown registers): 0 = all digital circuits running, outputs are active 1 = all digital circuits in power save mode, outputs muted 1 adcpd 1 adc powerdown: 0 = adc enabled 1 = adc disabled 0011010 (1ah) powerdown control 5:2 dacpd[3:0] 1111 dac powerdowns (0 = dac enabled, 1 = dac disabled) dacpd[0] = dac1 dacpd[1] = dac2 dacpd[2] = dac3 dacpd[3] = dac4
pre-production wm8777 w pp rev 3.0 january 2005 81 register address bit label default description 6 spdiftxd 1 spdif_tx powerdown 0 = spdif_tx enabled 1 = spdif_tx disabled 7 spdifrxd 1 spdif_rx powerdown 0 = spdif_rx enabled 1 = spdif_rx disabled 8 oscpd 1 osc power down 0 = oscillator enabled 1 = oscillator disabled 1:0 paiftx_fmt [1:0] 10 interface format select 00 = right justified mode 01 = left justified mode 10 = i 2 s mode 11 = dsp (early or late) mode pdataoplrc polarity or dsp early/late mode select 2 paiftx_lrp 0 left justified / right justified / i 2 s 0 =standard pdataoplrc polarity 1 =inverted pdataoplrc polarity dsp mode 0 = early dsp mode 1 = late dsp mode 3 paiftx_bcp 0 adcpbclk/pbclk polarity 0 = normal adcpbclk/pbclk. 1 = inverted adcpbclk/pbclk. 5:4 paiftx_wl [1:0] 10 input word length 00 = 16-bit mode 01 = 20-bit mode 10 = 24-bit mode 11 = 32-bit mode (not supported in right justified mode) 6 adchpd 0 adc highpass filter disable: 0 = highpass filter enabled 1 = highpass filter disabled 7 adcosr 0 adc oversample rate select 0 = 128x oversampling 1 = 64x oversapmling 0011011 (1bh) primary interface control (tx) 8 sync 0 sync adc and dac together. 0 = enable sync function 1 = disable sync function 3:0 lct[3:0] 1011 (-6db) limiter threshold/alc target level in 1db steps. 0000: -16db fs 0001: -15db fs 1101: -3db fs 1110: -2db fs 1111: -1db fs 6:4 maxgain[2:0] 111 (+24db) set maximum gain of pga 111 = +24db 110 = +20db .(-4db steps) 010 = +4db 001 = 0db 000 = 0db 0011101 (1dh) alc control 1 8:7 lcsel[1:0] 00 (off) alc/limiter function select 00 = limiter 01 = alc right channel only 10 = alc left channel only 11 = alc stereo (pga registers unused)
wm8777 pre-production w pp rev 3.0 january 2004 82 register address bit label default description 3:0 hld[3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms (time doubles with every step) 1111 = 43.691s 7 alczc 0 alc zero cross detection circuit. 0 = zero cross detection disabled. 1 = zero cross detection enabled. 0011110 (1eh) alc control 2 8 lcen 0 enable the pga gain control circuit. 0 = pga gain control disabled 1 = pga gain control enabled alc/limiter attack (gain ramp down) time 3:0 atk[3:0] 0010 (33ms/1ms) acl mode 0000 = 8.4ms 0001 = 16.8ms 0010 = 33.6ms.. (time doubles with every step) 1010 or higher = 8.6s limiter mode 0000 = 250us 0001 = 500us 0010 = 1ms (time doubles with every step) 1010 or higher = 256ms alc/limiter decay (gain ramp up) time 7:4 dcy[3:0] 0011 acl mode 0000 = 33.5ms 0001 = 67.2ms 0010 = 134.4ms.. (time doubles with every step) 1010 or higher = 34.41s limiter mode 0000 = 1.2ms 0001 = 2.4ms 0010 = 4.8ms (time doubles with every step) 1010 or higher = 1.2288s frequency dependant decay enable (limiter only) 0 = frequency dependent decay disabled 1 = frequency dependent decay enabled dcy 20khz input (or disabled) 1khz input 0011111 (1fh) alc control 3 8 fdecay 0 0000 0001 0010 .. 1010 or higher 1.2ms 2.4ms 4.8ms .. 1.2288s 24ms 48ms 96ms .. 24.576s 0 ngat 0 noise gate enable (alc only) 0 = noise gate disabled 1 = noise gate enabled 0100000 (20h) noise gate control 4:2 ngth[2:0] 000 noise gate threshold 000 = -78dbfs 001 = -72dbfs 6 db steps 110 = -42dbfs 111 = -36dbfs maximum attenuation of pga 0100001 (21h) limiter control 3:0 maxatten [3:0] 0110 alc (lower pga gain limit) 1010 or lower = -1db 1011 = -5db (-4db steps) 1110 = -17db 1111 = -21db limiter (attenuation below static) 0000 = -3db 0001 = -4db 0010 = -5db . (-1db steps) 1001 = -12db
pre-production wm8777 w pp rev 3.0 january 2005 83 register address bit label default description 6:4 tranwin [2:0] 010 length of transient window 000 = 0us (disabled) 001 = 62.5us 010 = 125us .. 111 = 4ms 1:0 ftrbl[1:0] 00 control treble boost and cut:- 00 = both off ( amps disabled) 01 = treble cut 10 = treble boosted 11 = both off (amps enabled) 3:2 fbass[1:0] 00 controls bass boost and cut:- 00 = both off (amps disabled) 01 = bass cut 10 = bass boosted 11 = both off (amps enabled) 4 fbm 0 bass managed signal path select 0 = path disabled 1 = path enabled 5 fbyp 0 bypass signal path select 0 = path disabled 1 = path enabled 0100010 (22h) front mixer control 1 6 ain6 0 0 = ain6 not selected 1 = ain6 applied to front channels 2:0 flfegain[2:0] 000 front lfe gain: 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db 3 flfe 0 lfe signal path select 0 = path disabled 1 = path enabled 6:4 cntrgain[2:0] 000 front cntr gain: 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db 0100011 (23h) front mixer control 2 7 cntr 0 center signal path mix 0 = path disabled 1 = path enabled 0100100 (24h) front mixer control 3 2:0 reargain[2:0] 000 front rear gain: 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db
wm8777 pre-production w pp rev 3.0 january 2004 84 register address bit label default description 3 rear 0 rear signal path mix 0 = path disabled 1 = path enabled 1:0 ctrbl[1:0] 00 control treble boost and cut: 00 = both off (amps disabled) 01 = treble cut 10 = treble boosted 11 = both off (amps enabled) 3:2 cbass[1:0] 00 controls bass boost and cut:- 00 = both off (amps disabled) 01 = bass cut 10 = bass boosted 11 = both off (amps enabled) 4 cbm 0 bass managed signal path select 0 = path disabled 1 = path enabled 5 cbyp 0 bypass signal path select 0 = path disabled 1 = path enabled 0100101 (25h) center mixer control 1 6 hpsel 0 controls headphone output mux:- 0 = frontl/r output on headphone channels 1 = auxl/r output on headphone channels 2:0 clfegain[2:0] 000 center lfe gain: 000 = 0db 001 = 1db 010 = 2db 011 = 3db 100 = 4db 101 = 4.5db 110 = 5db 111 = 6db 0100110 (26h) center mixer control 2 3 clfe 0 lfe signal path select: 0 = path disabled 1 = path enabled 0 auxlbyp 0 bypass select for aux left output 0 = bass managed 1 = bypass 1 auxrbyp 0 bypass select for aux right output 0 = bass managed 1 = bypass 2 surlbyp 0 bypass select for surround left output 0 = bass managed 1 = bypass 0100111 (27h) bass management bypass 3 surrbyp 0 bypass select for surround right output 0 = bass managed 1 = bypass 3:0 fbass[3:0] 0000 gain control for bass boost/cut C see table 3 0101000 (28h) front bass control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain front bass in intermediate latch (no change to output) 1 = store gain front bass and update attenuation on all channels. 0101001 3:0 ftreb[3:0] 0000 gain control for bass boost/cut C see table 3
pre-production wm8777 w pp rev 3.0 january 2005 85 register address bit label default description (29h) front treble control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain front treble in intermediate latch (no change to output) 1 = store gain front treble and update attenuation on all channels. 3:0 cbass[3:0] 0000 gain control for bass boost/cut C see table 3 0101010 (2ah) center bass control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain center bass in intermediate latch (no change to output) 1 = store gain center bass and update attenuation on all channels. 3:0 ctreb[3:0] 0000 gain control for bass boost/cut C see table 3 0101011 (2bh) center treble control 8 update not latched controls simultaneous update of all attenuation latches 0 = store gain center treble in intermediate latch (no change to output) 1 = store gain center treble and update attenuation on all channels. 1:0 cntp[1:0] 00 pregain control for cntr control channel 00 = 0db attenuation 01 = -6db attenuation 10 = -12db attenuation 11 = -18db attenuation 3:2 ftrp[1:0] 00 pregain control for frontr tone control channel 00 = 0db attenuation 01 = -6db attenuation 10 = -12db attenuation 11 = -18db attenuation 5:4 ftlp[1:0] 00 pregain control for frontl tone control channel 00 = 0db attenuation 01 = -6db attenuation 10 = -12db attenuation 11 = -18db attenuation 6 updatec 0 controls simultaneous update of all attenuation latches 0 = store pregain cntr in intermediate latch (no change to output) 1 = store pregain cntr and update attenuation on all channels. 7 updater 0 controls simultaneous update of all attenuation latches 0 = store pregain right in intermediate latch (no change to output) 1 = store pregain right and update attenuation on all channels. 0101100 (2ch) mixer pregain 8 updatel 0 controls simultaneous update of all attenuation latches 0 = store pregain left in intermediate latch (no change to output) 1 = store pregain left and update attenuation on all channels. 0 auxlpd 1 auxiliary left output powerdown. 0 = powerup 1 = powerdown 1 auxrpd 1 auxiliary left output powerdown. 0 = powerup 1 = powerdown 0101101 (2dh) output powerdown 2 surlpd 1 surround left output powerdown. 0 = powerup 1 = powerdown
wm8777 pre-production w pp rev 3.0 january 2004 86 register address bit label default description 3 surrpd 1 surround right output powerdown. 0 = powerup 1 = powerdown 4 lfepd 1 lfe output powerdown. 0 = powerup 1 = powerdown 5 ctrpd 1 center output powerdown. 0 = powerup 1 = powerdown 6 frtlpd 1 front left output powerdown. 0 = powerup 1 = powerdown 7 frtrpd 1 front right output powerdown. 0 = powerup 1 = powerdown 8 hppd 1 headphone output powerdown. 0 = powerup 1 = powerdown 7:0 lag[7:0] 11001111 (0db) attenuation control for left channel adc gain in 0.5db steps. see table 68 0101110 (2eh) attenuation adc left 8 zclen 0 zero cross enable for left channel adc 0 = disable zero cross 1 = enable zero cross 7:0 rag[7:0] 11001111 (0db) attenuation control for right channel adc gain in 0.5db steps. see table 68 0101111 (2fh) attenuation adc right 8 zcren 0 zero cross enable for right channel adc 0 = disable zero cross 1 = enable zero cross 0 mutel 0 left channel mute control 0 = channel not muted 1 = channel muted 1 muter 0 left channel mute control 0 = channel not muted 1 = channel muted 2 adcatc 0 attenuator control 0 = adc use attenuations as programmed. 1 = right channel adc use corresponding left adc attenuations 0110000 (30h) attenuation control 3 toadc 0 time out clock enable/disable 0 = time out clock enabled. 1 = time out clock disabled.
pre-production wm8777 w pp rev 3.0 january 2005 87 register address bit label default description 5:0 ain[5:0] 00000 adc left channel input mux control bits 00000 = ute 00001 = ain1 00010 = ain2 00011 = ain1 + ain2 11111 = ain1 + ain2 + ain3 + ain4 + ain5 + ain6 0110001 (31h) adc mux and powerdown control 8 ainpd 1 input mux and buffer powerdown 0 = input mux and buffer enabled 1 = input mux and buffer powered down 2:0 mx1[2:0] 001 vout1 output select (see figure 28) 5:3 mx2[2:0] 001 vout2 output select (see figure 28) 7 outpd1 1 mixer powerdown select 0 = powerup 1 = powerdown 0110010 (32h) output mux and powerdown control 1 8 outpd2 1 mixer powerdown select 0 = powerup 1 = powerdown 2:0 mx3[2:0] 001 vout3 output select (see figure 28) 4:3 mx4[1:0] 01 vout4 output select (see figure 29) 7 outpd3 1 mixer powerdown select 0 = powerup 1 = powerdown 0110011 (33h) output mux and powerdown control 2 8 outpd4 1 mixer powerdown select 0 = powerup 1 = powerdown 0110100 (34h) pll control 1 8:0 pll_k[8:0] 121 (hex) fractional (k) part of pll input/output frequency ratio (bits 8:0). 0110101 (35h) pll control 2 8:0 pll_k[17:9] 17e (hex) fractional (k) part of pll input/output frequency ratio (bits 17:9). 3:0 pll_k[21:18] d(hex) fractional (k) part of pll input/output frequency ratio (bits 21:18) 4 clkoutsrc 0 clkout pin source:- 0 = pll clock output 1 = crystal clock output. 6 pll2dac 0 dac clock source 0 = mclk pin 1 = pll clock 7 pll2adc 0 adc clock source 0 = mclk or adcmlck pin 1 = pll clock 0110110 (36h) pll control 3 8 pll2tx 1 s/pdif tx clock source 0 = mlck or adcmclk pin 1 = pll clock 0 pllpd 1 0 = enable pll 1 = disable pll 1 postscale 0 0 = no post scale 1= divide mclk by 2 after pll 2 frac_en 0 0 = integer n only pll 1 = integer n and fractional k pll 3 prescale 0 0 = no pre-scale 1 = divide mclk by 2 prior to pll 0110111 (37h) pll control 4 8:4 pll_n[4:0] 00000 integer (n) divisor part of pll input/output frequency ratio. use values greater than 5 and less than 13.
wm8777 pre-production w pp rev 3.0 january 2004 88 register address bit label default description 1:0 dac1sel[1:0] 00 3:2 dac2sel[1:0] 01 5:4 dac3sel[1:0] 10 0111000 (38h) dac digital input selector 7:6 dac4sel[1:0] 11 dac digital input select. 00 = dac takes data from pdataip1 01 = dac takes data from pdataip2 10 = dac takes data from pdataip3 11 = dac takes data from pdataip4 0 con/pro 0 0 = consumer mode 1 = professional mode (not supported by wm8777) 1 audio_n 0 0 = s/pdif transmitted data is audio pcm. 1 = s/pdif transmitted data is not audio pcm. 2 cpy_n 0 0 = transmitted data has copyright asserted. 1 = transmitted data has no copyright assertion. 5:3 preemph[2:0] 000 000 = data from audio interface has no pre-emphasis. 001 = data from audio interface has pre-emphasis. 010 = reserved (audio interface has pre-emphasis). 011 = reserved (audio interface has pre-emphasis). all other modes are reserved and should not be used. 0111001 (39h) s/pdif transmitter channel bit control 1 7:6 chstmode[1:0] 00 s/pdif channel status bits. 00 = only valid mode for consumer applications. all other modes are reserved. 0111010 (3ah) s/pdif transmitter channel bit control 2 7:0 catcode[7:0] 00000000 category code. refer to s/pdif specification for details. 00h indicates general mode. 3:0 srcnum[3:0] 0000 source number. no definitions are attached to data. see s/pdif specification for details. channel number for subframe 1 chnum1 channel status bits[23:20] 00 0000: do not use channel number 01 0001: send to left channel 10 0010: send to right channel 5:4 chnum1[1:0] 00 11 0000: do not use channel number channel number for subframe 2 chnum2 channel status bits[23:20] 00 0000: do not use channel number 01 0001: send to left channel 10 0010: send to right channel 0111011 (3bh) s/pdif transmitter channel bit control 3 7:6 chnum2[1:0] 00 11 0000: do not use channel number 3:0 freq[3:0] 0001 sampling frequency. see s/pdif specification for details. 0001 = sampling frequency not indicated. 0111100 (3ch) s/pdif transmitter channel bit control 4 5:4 clkacu[1:0] 11 clock accuracy of generated clock. 00 = level ii 01 = level i 10 = level iii 11 = interface frame rate not matched to sampling frequency. 0111101 (3dh) s/pdif 0 maxpaifrx_wl 1 maximum audio sample word length 0 = 20 bits 1 = 24 bits
pre-production wm8777 w pp rev 3.0 january 2005 89 register address bit label default description audio sample word length. 000 = word length not indicated txpaifrx_wl maxpaifrx_wl= =1 maxpaifrx_wl= =0 001 20 bits 16 bits 010 22 bits 18 bits 100 23 bits 19 bits 101 24 bits 20 bits 110 21 bits 17 bits 3:1 txpaifrx_wl [2:0] 101 all other combinations reserved 7:4 orgsamp[3:0] 0000 original sampling frequency. see s/pdif specification for details. 0000 = original sampling frequency not indicated 1:0 saif_fmt [1:0] 10 secondary audio interface format select 00 = right justified mode 01 = left justified mode 10 = i 2 s mode 11 = dsp (early or late) mode slrclk polarity or dsp early/late mode select 2 saif_lrp 0 left justified / right justified/ i 2 s 0 = standard pdataiplrc polarity 1 = inverted pdataiplrc polarity dsp mode 0 = early dsp mode 1 = late dsp mode 3 saif_bcp 0 sbclk polarity 0 = normal sbclk. 1 = inverted sbclk. 0111110 (3eh) secondary interface control 5:4 saif_wl [1:0] 10 input word length 00 = 16-bit mode 01 = 20-bit mode 10 = 24-bit mode 11 = 32-bit mode (not supported in right justified mode) 2:0 saifrate[2:0] 010 master mode mclk:slrc ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs 3 sms 0 maser/slave interface mode select 0 = slave mode C slrc and sbclk are inputs 1 = master mode C slrc and sbclk are outputs 0111111 (3fh) secondary interface master mode control 5:4 saifclksrc[1:0] 00 audio interface master clock source when sms is 1. 00 = mclk 01 = gpio (if a dcclksrc is set) 10 = pll clock 11 = pll clock 1000000 (40h) s/pdif receiver 0 spdinmode 0 selects the input circuit type for the s/pdif input 0 = normal cmos input 1 = comparator input. compatible with 200mv ac coupled consumer s/pdif input signals.
wm8777 pre-production w pp rev 3.0 january 2004 90 register address bit label default description 5:4 rxinsel[1:0] 00 s/pdif receiver input mux select. note that the general purpose inputs must be configured using gpioxop to be either cmos or comparator inputs if selected by rxinsel. 00 = s/pdif_in1 01 = s/pdif_in2 (gpio1) 10 = s/pdif_in3 (gpio2) 11 = s/pdif_in4 (gpio3) 6 fillmode 0 determines what spdif_rx should do if the validity bit indicates invalid data: 0 = data from spdif_rx remains static at last valid sample. 1 = data from spdif_rx is output as all zeros. 7 alwaysvalid 0 used to override the recovered validity bit. 0 = use validity bit. 1 = ignore validity bit. input selector 8 adcclksrc 0 adc clock source 0 = adcmclk is from mclk pin and adcpbclk is from pbclk pin 1 = adcmclk is from gpio1, and adpbclk is from gpio2. (note that when in this mode rxinsel must not be set to 01 or 10.) 0 rx2dac 0 received s/pdif pcm data to dac. 0 = dac1 takes data from primary audio interface. 1 = dac1 takes data from s/pdif receiver. 2:1 txsrc[1:0] 00 s/pdif transmitter data source. 00 = s/pdif received data. 01 = adc digital output data. 10 = secondary audio interface received data 11 = dac audio interface received data. 3 txrxthru 0 only used if txsrc==00. configures only the channel bit in the s/pdif frame. 0 = channel data equal to recovered channel data. 1 = channel data taken from channel status registers. 5:4 paifsrc[1:0] 01 audio interface output source 00 = s/pdif received data 01 = adc digital output data 10 = secondary audio interface received data 11 = power-down primary audio interface transmitter 1000001 (41h) interface source select 7:6 saifsrc[1:0] 00 secondary audio interface transmitter data source. 00 = s/pdif received data. 01 = adc digital output data. 10 = power-down secondary audio interface transmitter 11 = primary audio interface received data. 1000010 (42h) s/pdif data/clock recovery 5:3 fpll[2:0] 111 select jitter attenuation bandwidth. 000 = invalid 001 = 28.84hz 010 = 14.92hz 011 = 7.46hz 100 = 3.73hz 101 = 1.87hz 110 = 0.97hz 111 = 0.47hz
pre-production wm8777 w pp rev 3.0 january 2005 91 register address bit label default description 3:0 gpio1op[3:0] 0000 0000 = int 0001 = v - validity 0010 = u - user data bit 0011 = c - channel status data 0100 = p - parity bit 0101 = non-audio (audio_n || pcm_n) 0110 = unlock 0111 = csud (channel status registers updated) 1000 = zero flag 1 output 1001 = zero flag 2 output 1010 = gpio1set as s/pdif input (standard cmos input buffer) 1011 = gpio1set as s/pdif input (comparator input for ac coupled consumer s/pdif signals) 1100 = sub frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = start of block signal 1000111 (47h) gpio control 1 7:4 gpio2op[3:0] 0001 0000 = int 0001 = v - validity 0010 = u - user data bit 0011 = c - channel status data 0100 = p - parity bit 0101 = non-audio (audio_n || pcm_n) 0110 = unlock 0111 = csud (channel status registers updated) 1000 = zero flag 1 output 1001 = zero flag 2 output 1010 = gpio2set as s/pdif input (standard cmos input buffer) 1011 = gpio2set as s/pdif input (comparator input for ac coupled consumer s/pdif signals) 1100 = sub frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = start of block signal 1001000 (48h) gpio control 2 3:0 gpio3op[3:0] 0010 0000 = int 0001 = v - validity 0010 = u - user data bit 0011 = c - channel status data 0100 = p - parity bit 0101 = non-audio (audio_n || pcm_n) 0110 = unlock 0111 = csud (channel status registers updated) 1000 = zero flag 1 output 1001 = zero flag 2 output 1010 = gpio3set as s/pdif input (standard cmos input buffer) 1011 = gpio3set as s/pdif input (comparator input for ac coupled consumer s/pdif signals) 1100 = sub frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = start of block signal
wm8777 pre-production w pp rev 3.0 january 2004 92 register address bit label default description 7:4 gpomodeop [3:0] 1010 0000 = int 0001 = v - validity 0010 = u - user data bit 0011 = c - channel status data 0100 = p - parity bit 0101 = non-audio (audio_n || pcm_n) 0110 = unlock 0111 = csud (channel status registers updated) 1000 = zero flag 1 output 1001 = zero flag 2 output 1010 = not used 1011 = not used 1100 = sub frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = start of block signal 1001001 (49h) s/pdif receiver error mask 7:0 mask[7:0] 0000000 when a lag is masked, it does not update the error register or contribute to the interrupt pulse. 0 = unmask, 1 = mask. mask[0] = mask control for unlock mask[1] = mask control for validity mask[2] = mask control for parityerr mask[3] = mask control for bip mask[4] = mask control for audio_n mask[5] = mask control for pcm_n mask[6] = mask control for cpy_n mask[7] = mask control for spdif_mode 4 readen3 0 3-wire read-back mode enable. 0 = 3-wire read-back mode disabled 1 = 3-wire read-back mode enabled 1001010 (4ah) read-back control 5 readen2 0 2-wire read-back mode enable. 0 = 2-wire read-back mode disabled 1 = 2-wire read-back mode enabled 0 unlock pll unlock signal. 0 = pll is locked to incoming s/pdif stream. 1 = pll is not locked to the incoming s/pdif stream. 1 validity v bit from s/pdif input stream. 0 = data word is valid. 1 = data word is not valid. 2 parityerr even parity check. 0 = no parity errors detected. 1 = parity error detected. 3 bip biphase coding of s/pdif input stream. 0 = biphase coding is correct. 1 = biphase coding error detected. 4 audio_n received channel status bit 1 has changed. 0 = normal running. 1 = change on audio_n. 5 pcm_n pcm_n bit has changed 0 = normal running. 1 = change on pcm_n. 1001011 (4bh) s/pdif receiver error register (read-only) 6 cpy_n received channel status bit 2 has changed. 0 = normal running. 1 = change on cpy_n.
pre-production wm8777 w pp rev 3.0 january 2005 93 register address bit label default description 7 spdif_mode s/pdif mode change. 0: normal running 1: change in s/pdif frequency mode detected. 0 con/pro recovered s/pdif channel status bit 0. 0 = consumer mode 1 = professional mode the wm8777 is a consumer mode device. detection of professional mode may give erroneous behavior. 1 audio_n recovered s/pdif channel status bit 1. 0 = data word represents audio pcm samples. 1 = data word does not represent audio pcm samples. 2 cpy_n recovered s/pdif channel status bit 2. 0 = copyright is asserted for this data. 1 = copyright is not asserted for this data. 3 deemph recovered s/pdif channel status bit 3. 0 = recovered s/pdif data has no pre-emphasis. 1 = recovered s/pdif data has pre-emphasis. 5:4 reserved recovered s/pdif channel status bits[5:4]. reserved for additional de-emphasis modes. 1001100 (4ch) s/pdif receiver channel status register 1 (read-only) 7:6 chstmode[1:0] recovered s/pdif channel status bits[7:6]. 00 = only valid mode for consumer applications. all other modes reserved. 1001101 (4dh) s/pdif receiver channel status register 2 (read-only) 7:0 catcode[7:0] recovered s/pdif channel status bits[15:8] - category code. refer to s/pdif specification for details. 00h indicates general mode. 3:0 srcnum[3:0] recovered s/pdif channel status bits[19:16] - indicates number of s/pdif source. 1001110 (4eh) s/pdif receiver channel status register 3 (read-only) 7:4 chnum1[3:0] recovered s/pdif channel status bits[23:20] - channel number for channel 1. 0000 = take no account of channel number (channel 1 defaults to left dac) 0001 = channel 1 to left channel 0010 = channel 1 to right channel 3:0 freq[3:0] recovered s/pdif channel status bits[27:24] - sampling frequency. see s/pdif specification for details. 0001 = sampling frequency not indicated. 1001111 (4fh) s/pdif receiver channel status register 4 (read-only) 5:4 clkacu[1:0] recovered s/pdif channel status bits[29:28] - clock accuracy of received clock. 00 = level ii 01 = level i 10 = level iii 11 = interface frame rate not matched to sampling frequency. 0 maxpaifrx_wl recovered s/pdif channel status bit[32] - maximum audio sample word length 0 = 20 bits 1 = 24 bits recovered s/pdif channel status bits[35:33] - audio sample word length rxpaifrx_wl maxpaifrx_wl= =1 maxpaifrx_wl= =0 001 20 bits 16 bits 010 22 bits 18 bits 1010000 (50h) s/pdif receiver channel status register 5 (read-only) 3:1 rxpaifrx_wl [2:0] 100 23 bits 19 bits
wm8777 pre-production w pp rev 3.0 january 2004 94 register address bit label default description 101 24 bits 20 bits 110 21 bits 17 bits all other combinations are reserved and may give erroneous operation. 7:4 orgsamp[3:0] recovered s/pdif channel status bits[39:36] - original sampling frequency. see s/pdif specification for details. 0000 = original sampling frequency not indicated 0 audio_n received channel status bit 1 0 = data word represents audio pcm samples. 1 = data word does not represent audio pcm samples. 1 pcm_n detects non-audio data from a 96-bit sync code, as defined in iec-61937. 0 = sync code not detected. 1 = sync code detected C received data is not audio pcm. 2 cpy_n recovered s/pdif channel status bit 2. 0 = copyright is asserted for this data. 1 = copyright is not asserted for this data. note this signal is inverted and will cause an interrupt on logic 0. 1010001 (51h) s/pdif status (read- only) 4:3 spdif_mode s/pdif frequency mode. 00: not supported 01: 88-96khz 10: 44-48khz 11: 32khz 1111111 (7fh) software reset 8:0 reset writing any value to this register will apply a reset to the device registers. table 82 register map description
pre-production wm8777 w pp rev 3.0 january 2005 95 digital filter characteristics parameter test conditions min typ max unit adc filter 0.01 db 0 0.4535fs passband -6db 0.5fs passband ripple 0.01 db stopband 0.5465fs stopband attenuation f > 0.5465fs -65 db group delay 22 fs dac filter 0.05 db 0.444fs passband -3db 0.487fs passband ripple 0.05 db stopband 0.555fs stopband attenuation f > 0.555fs -60 db group delay 16 fs table 83 digital filter characteristics
wm8777 pre-production w pp rev 3.0 january 2004 96 dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 32 dac digital filter frequency response C 44.1, 48 and 96khz -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 33 dac digital filter ripple C 44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 34 dac digital filter frequency response (with dacosr=1) C 192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 35 dac digital filter ripple (with dacosr=1) - 192khz adc filter responses -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 36 adc digital filter frequency response -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 37 adc digital filter ripple
pre-production wm8777 w pp rev 3.0 january 2005 97 adc high pass filter the wm8777 has a selectable digital highpass filter to remove dc offsets. the filter response is characterised by the following polynomial. figure 38 adc highpass filter response 1 - z -1 1 - 0.9995z -1 h(z) = -15 -10 -5 0 0 0.0005 0.001 0.0015 0.002 response (db) frequency (fs)
wm8777 pre-production w pp rev 3.0 january 2004 98 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 39 de-emphasis frequency response (32khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 40 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 41 de-emphasis frequency response (44.1khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 42 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 43 de-emphasis frequency response (48khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 44 de-emphasis error (48khz)
pre-production wm8777 w pp rev 3.0 january 2005 99 ain1l 10k 10uf ain2l 10k 10uf ain3l 10k 10uf ain7l 10k 10uf ain8l 10k 10uf ain1r 10k 10uf ain2r 10k 10uf ain3r 10k 10uf ain7r 10k 10uf ain8r 10k 10uf source selector inputs ainvgr ainopr 5k ainvgl ainopl 5k applications information external analogue input circuit configuration in order to allow the use of 2v rms and larger inputs to the adc and aux inputs, a structure is used that uses external resistors to drop these larger voltages. this also increases the robustness of the circuit to external abuse such as esd pulse. figure 45 shows the adc input multiplexor circuit with external components allowing 2vrms inputs to be applied. figure 45 adc input multiplexor confiuration figure 46 shows the 5.1channel input multiplexor configuration system aux 5.1 line inputs 4k mx1[1] mx1[0] mx1[2] 4k 4k 4k dac1l/r bypassl/r aux1l/r 4k mx2[1] mx2[0] 4k 4k dac2l/r dac3l/r 10uf 10uf aux2l/r 10uf aux3l/r 4k mx3[1] mx3[0] 4k 4k
wm8777 pre-production w pp rev 3.0 january 2004 100 external s/pdif input circuit configuration the spin, gpio1, gpio2, and gpio3 pads can be configured to accept either cmos or s/pdif input signals. in s/pdif mode an a.c. coupled input signal is applied to vin. a hysteresis comparator buffers this signal and converts it to cmos to drive on-chip. in cmos mode the s/pdif circuit is disabled and the signal is buffered using standard cmos logic. to allow an s/pdif signal to be received correctly the incoming signal must be a.c. coupled. the recommended off-chip input configuration for this is shown below: 0.1 ! 2 ? wm8777 rx vin
pre-production wm8777 w pp rev 3.0 january 2005 101 recommended analogue output external components it may be that a lowpass filter is required to be applied to the output from each dac channel for hi fi applications. typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta dac structure used in wm8777 produces much less high frequency output noise than competitors devices). this filter is typically also used to provide the 2x gain needed to provide the standard 2vrms output level from most consumer equipment. figure 47 shows a suitable post dac filter circuit, with 2x gain. alternative inverting filter architectures might also be used with as good results. figure 47 recommended post dac filter circuit 7.5k ? ? ? ? 1.8k ? ? ? ? 10uf 1.0nf 47k ? ? ? ? 4.7k ? ? ? ? 680pf 4.7k ? ? ? ? 51 op_fil vout1l op_fil vout1r op_fil vout2r op_fil vout2l op_fil vout3l op_fil vout3r op_fil vout4l op_fil vout4r
wm8777 pre-production w pp rev 3.0 january 2004 102 package dimensions dm036.a ft: 100 pin tqfp (14 x 14 x 1.0 mm) c l e1 d1 d e a a2 a1 seating plane -c- 0.1 c e b notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 ms-026, variation = aba. refer to this specification for further details. symbols dimensions (mm) min nom max a ----- ----- 1.60 a 1 0.05 ----- 0.15 a 2 1.35 1.40 1.45 b 0.17 0.22 0.27 c ----- ----- 0.17 d 16.00 d 1 14.00 e 16.00 e 1 14.00 e 0.50 bsc l 0.50 0.60 0.75 0 o 3.5 o 7 o tolerances of form and position ccc 0.08 ref: jedec.95, ms-026 1 25 26 50 51 74 100 75 15.80 14.05 13.95 15.80 13.95 16.20 11.05 16.20
pre-production wm8777 w pp rev 3.0 january 2005 103 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknopaifrx_wledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wms standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wms publication of information regarding any third partys products or services does not constitute wms approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wms products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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